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| author | David S. Miller <davem@davemloft.net> | 2016-02-01 18:44:07 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-02-01 18:44:07 -0800 |
| commit | b45efa30a626e915192a6c548cd8642379cd47cc (patch) | |
| tree | 90d8b43ebceb850b0e7852d75283aebbd2abbc00 /drivers/clocksource/clksrc-dbx500-prcmu.c | |
| parent | 7a26019fdecdb45ff784ae4e3b7e0cc9045100ca (diff) | |
| parent | 34229b277480f46c1e9a19f027f30b074512e68b (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Diffstat (limited to 'drivers/clocksource/clksrc-dbx500-prcmu.c')
| -rw-r--r-- | drivers/clocksource/clksrc-dbx500-prcmu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index b375106844d8..dfad6eb99662 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -12,8 +12,9 @@ * power domain. We use the Timer 4 for our always-on clock * source on DB8500. */ +#include <linux/of.h> +#include <linux/of_address.h> #include <linux/clockchips.h> -#include <linux/clksrc-dbx500-prcmu.h> #include <linux/sched_clock.h> #define RATE_32K 32768 @@ -63,9 +64,9 @@ static u64 notrace dbx500_prcmu_sched_clock_read(void) #endif -void __init clksrc_dbx500_prcmu_init(void __iomem *base) +static void __init clksrc_dbx500_prcmu_init(struct device_node *node) { - clksrc_dbx500_timer_base = base; + clksrc_dbx500_timer_base = of_iomap(node, 0); /* * The A9 sub system expects the timer to be configured as @@ -85,3 +86,5 @@ void __init clksrc_dbx500_prcmu_init(void __iomem *base) #endif clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); } +CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", + clksrc_dbx500_prcmu_init); |