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| author | Dave Airlie <airlied@gmail.com> | 2015-11-07 17:16:59 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2015-11-07 17:16:59 +1000 |
| commit | 816d2206f0f9953ca854e4ff1a2749a5cbd62715 (patch) | |
| tree | 26b8a56c4656a8794911c31246061bfe05d9cd9b /drivers/gpu/drm/i915/intel_pm.c | |
| parent | d0baf9218cacd9dd606c75f9961f94172b16de12 (diff) | |
| parent | 1b0e3a049efe471c399674fd954500ce97438d30 (diff) | |
Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel into drm-next
Here's a handful of i915 fixes for drm-next/v4.4. Imre's commit alone
should address the remaining warnings galore you experienced on
Skylake. Almost all of the rest are also fixes against user or QA
reported bugs, with references.
* tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel:
drm/i915/skl: disable display side power well support for now
drm/i915: Extend DSL readout fix to BDW and SKL.
drm/i915: Do graphics device reset under forcewake
drm/i915: Skip fence installation for objects with rotated views (v4)
drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015)
drm/i915/skl: Prevent unclaimed register writes on skylake.
drm/i915: disable CPU PWM also on LPT/SPT backlight disable
drm/i915: Fix maxfifo watermark calc on vlv cursor planes
drm/i915: add hotplug activation period to hotplug update mask
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9dda3eaebd12..d52a15df6917 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1135,7 +1135,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) case DRM_PLANE_TYPE_CURSOR: for (level = 0; level < wm_state->num_levels; level++) wm_state->sr[level].cursor = - wm_state->sr[level].cursor; + wm_state->wm[level].cursor; break; case DRM_PLANE_TYPE_PRIMARY: for (level = 0; level < wm_state->num_levels; level++) @@ -2818,7 +2818,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, int plane; u32 val; + memset(ddb, 0, sizeof(*ddb)); + for_each_pipe(dev_priv, pipe) { + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) + continue; + for_each_plane(dev_priv, pipe, plane) { val = I915_READ(PLANE_BUF_CFG(pipe, plane)); skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], |