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| author | James Morris <james.l.morris@oracle.com> | 2014-11-19 21:32:12 +1100 |
|---|---|---|
| committer | James Morris <james.l.morris@oracle.com> | 2014-11-19 21:32:12 +1100 |
| commit | b10778a00d40b3d9fdaaf5891e802794781ff71c (patch) | |
| tree | 6ba4cbac86eecedc3f30650e7f764ecf00c83898 /drivers/mfd/intel_msic.c | |
| parent | 594081ee7145cc30a3977cb4e218f81213b63dc5 (diff) | |
| parent | bfe01a5ba2490f299e1d2d5508cbbbadd897bbe9 (diff) | |
Merge commit 'v3.17' into next
Diffstat (limited to 'drivers/mfd/intel_msic.c')
| -rw-r--r-- | drivers/mfd/intel_msic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mfd/intel_msic.c b/drivers/mfd/intel_msic.c index 049fd23af54a..443e7cddff28 100644 --- a/drivers/mfd/intel_msic.c +++ b/drivers/mfd/intel_msic.c @@ -27,7 +27,7 @@ /* * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE. - * Since IRQ block starts from address 0x002 we need to substract that from + * Since IRQ block starts from address 0x002 we need to subtract that from * the actual IRQ status register address. */ #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2)) |