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authorJames Morris <james.l.morris@oracle.com>2012-06-10 22:52:10 +1000
committerJames Morris <james.l.morris@oracle.com>2012-06-10 22:52:10 +1000
commit66dd07b88a1c9d446f32253da606b87324fa620e (patch)
tree4e0971bdd543585c7ab46716ae808a7fd82f9c35 /include/linux/spi/eeprom.h
parentf52c44cd27b4a0be37ef97f0466e4095ebebef3f (diff)
parentcfaf025112d3856637ff34a767ef785ef5cf2ca9 (diff)
Merge commit 'v3.5-rc2' into next
Diffstat (limited to 'include/linux/spi/eeprom.h')
-rw-r--r--include/linux/spi/eeprom.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/spi/eeprom.h b/include/linux/spi/eeprom.h
index 306e7b1c69ed..403e007aef68 100644
--- a/include/linux/spi/eeprom.h
+++ b/include/linux/spi/eeprom.h
@@ -20,6 +20,16 @@ struct spi_eeprom {
#define EE_ADDR3 0x0004 /* 24 bit addrs */
#define EE_READONLY 0x0008 /* disallow writes */
+ /*
+ * Certain EEPROMS have a size that is larger than the number of address
+ * bytes would allow (e.g. like M95040 from ST that has 512 Byte size
+ * but uses only one address byte (A0 to A7) for addressing.) For
+ * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
+ * is used. This instruction bit is normally defined as don't care for
+ * other AT25 like chips.
+ */
+#define EE_INSTR_BIT3_IS_ADDR 0x0010
+
/* for exporting this chip's data to other kernel code */
void (*setup)(struct memory_accessor *mem, void *context);
void *context;