diff options
| author | NeilBrown <neilb@suse.com> | 2015-09-05 11:07:04 +0200 |
|---|---|---|
| committer | NeilBrown <neilb@suse.com> | 2015-09-05 11:08:32 +0200 |
| commit | e89c6fdf9e0eb1b5a03574d4ca73e83eae8deb91 (patch) | |
| tree | f9df292ed03a5a3c4ddc658ae3646f02a1ffafce /include/linux/usb/chipidea.h | |
| parent | c3cce6cda162eb2b2960a85d9c8992f4f3be85d0 (diff) | |
| parent | 1081230b748de8f03f37f80c53dfa89feda9b8de (diff) | |
Merge linux-block/for-4.3/core into md/for-linux
There were a few conflicts that are fairly easy to resolve.
Signed-off-by: NeilBrown <neilb@suse.com>
Diffstat (limited to 'include/linux/usb/chipidea.h')
| -rw-r--r-- | include/linux/usb/chipidea.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index ab94f78c4dd1..a41833cd184c 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -19,8 +19,11 @@ struct ci_hdrc_platform_data { enum usb_phy_interface phy_mode; unsigned long flags; #define CI_HDRC_REGS_SHARED BIT(0) +#define CI_HDRC_DISABLE_DEVICE_STREAMING BIT(1) #define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2) -#define CI_HDRC_DISABLE_STREAMING BIT(3) +#define CI_HDRC_DISABLE_HOST_STREAMING BIT(3) +#define CI_HDRC_DISABLE_STREAMING (CI_HDRC_DISABLE_DEVICE_STREAMING | \ + CI_HDRC_DISABLE_HOST_STREAMING) /* * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1, * but otg is not supported (no register otgsc). @@ -29,12 +32,22 @@ struct ci_hdrc_platform_data { #define CI_HDRC_IMX28_WRITE_FIX BIT(5) #define CI_HDRC_FORCE_FULLSPEED BIT(6) #define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7) +#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8) +#define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) +#define CI_HDRC_OVERRIDE_TX_BURST BIT(10) +#define CI_HDRC_OVERRIDE_RX_BURST BIT(11) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 void (*notify_event) (struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; + struct usb_otg_caps ci_otg_caps; bool tpl_support; + /* interrupt threshold setting */ + u32 itc_setting; + u32 ahb_burst_config; + u32 tx_burst_size; + u32 rx_burst_size; }; /* Default offset of capability registers */ |