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Diffstat (limited to 'arch/arm/plat-omap/include/syslink/ducatienabler.h')
| -rw-r--r-- | arch/arm/plat-omap/include/syslink/ducatienabler.h | 291 |
1 files changed, 291 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/syslink/ducatienabler.h b/arch/arm/plat-omap/include/syslink/ducatienabler.h new file mode 100644 index 000000000000..09212f58738d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ducatienabler.h @@ -0,0 +1,291 @@ +/* + * ducatienabler.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef _DDUCATIMMU_ENABLER_H_ +#define _DDUCATIMMU_ENABLER_H_ + +#include <linux/types.h> +#include <linux/mm.h> + +#include <syslink/hw_defs.h> +#include <syslink/hw_mmu.h> + + +#define PAGE_SIZE_4KB 0x1000 +#define PAGE_SIZE_64KB 0x10000 +#define PAGE_SIZE_1MB 0x100000 +#define PAGE_SIZE_16MB 0x1000000 + +/* Define the Peripheral PAs and their Ducati VAs. */ +#define L4_PERIPHERAL_MBOX 0x4A0F4000 +#define DUCATI_PERIPHERAL_MBOX 0xAA0F4000 + +#define L4_PERIPHERAL_I2C1 0x48070000 +#define DUCATI_PERIPHERAL_I2C1 0xA8070000 +#define L4_PERIPHERAL_I2C2 0x48072000 +#define DUCATI_PERIPHERAL_I2C2 0xA8072000 +#define L4_PERIPHERAL_I2C3 0x48060000 +#define DUCATI_PERIPHERAL_I2C3 0xA8060000 + +#define L4_PERIPHERAL_DMA 0x4A056000 +#define DUCATI_PERIPHERAL_DMA 0xAA056000 + +#define L4_PERIPHERAL_GPIO1 0x4A310000 +#define DUCATI_PERIPHERAL_GPIO1 0xAA310000 +#define L4_PERIPHERAL_GPIO2 0x48055000 +#define DUCATI_PERIPHERAL_GPIO2 0xA8055000 +#define L4_PERIPHERAL_GPIO3 0x48057000 +#define DUCATI_PERIPHERAL_GPIO3 0xA8057000 + +#define L4_PERIPHERAL_GPTIMER3 0x48034000 +#define DUCATI_PERIPHERAL_GPTIMER3 0xA8034000 +#define L4_PERIPHERAL_GPTIMER4 0x48036000 +#define DUCATI_PERIPHERAL_GPTIMER4 0xA8036000 +#define L4_PERIPHERAL_GPTIMER9 0x48040000 +#define DUCATI_PERIPHERAL_GPTIMER9 0xA8040000 +#define L4_PERIPHERAL_GPTIMER11 0x48088000 +#define DUCATI_PERIPHERAL_GPTIMER11 0xA8088000 + +#define L4_PERIPHERAL_UART1 0x4806A000 +#define DUCATI_PERIPHERAL_UART1 0xA806A000 +#define L4_PERIPHERAL_UART2 0x4806C000 +#define DUCATI_PERIPHERAL_UART2 0xA806C000 +#define L4_PERIPHERAL_UART3 0x48020000 +#define DUCATI_PERIPHERAL_UART3 0xA8020000 +#define L4_PERIPHERAL_UART4 0x4806E000 +#define DUCATI_PERIPHERAL_UART4 0xA806E000 + + +#define L3_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_LEN 0x20000000 + + + +#if 0 /* Original definitions for OMAP4430. */ +/* Define the various Ducati Memory Regions. */ +/* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */ +/* three pages are not used and are mapped to minimize number of PTEs */ +#define DUCATI_BOOTVECS_ADDR 0x1000 +#define DUCATI_BOOTVECS_LEN 0x3000 + +#define DUCATI_EXTMEM_SYSM3_ADDR 0x4000 +#define DUCATI_EXTMEM_SYSM3_LEN 0x1FC000 + +#define DUCATI_EXTMEM_APPM3_ADDR 0x10000000 +#define DUCATI_EXTMEM_APPM3_LEN 0x200000 + +#define DUCATI_PRIVATE_SYSM3_DATA_ADDR 0x84000000 +#define DUCATI_PRIVATE_SYSM3_DATA_LEN 0x200000 + +#define DUCATI_PRIVATE_APPM3_DATA_ADDR 0x8A000000 +#define DUCATI_PRIVATE_APPM3_DATA_LEN 0x200000 + +#define DUCATI_SHARED_M3_DATA_ADDR 0x90000000 +#define DUCATI_SHARED_M3_DATA_LEN 0x100000 + +#define DUCATI_SHARED_IPC_ADDR 0x98000000 +#define DUCATI_SHARED_IPC_LEN 0x100000 + +#define DUCATI_SW_DMM_ADDR 0x80000000 +#define DUCATI_SW_DMM_LEN 0x400000 +#endif + +/* OMAP4430 SDC definitions */ +#define L4_PERIPHERAL_L4CFG 0x4A000000 +#define DUCATI_PERIPHERAL_L4CFG 0xAA000000 + +#define L4_PERIPHERAL_L4PER 0x48000000 +#define DUCATI_PERIPHERAL_L4PER 0xA8000000 + +#define L3_IVAHD_CONFIG 0x5A000000 +#define DUCATI_IVAHD_CONFIG 0xBA000000 + +#define L3_IVAHD_SL2 0x5B000000 +#define DUCATI_IVAHD_SL2 0xBB000000 + +#define L3_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_LEN 0x10000000 + +#define L3_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_LEN 0x8000000 + +#define DUCATI_BOOTVECS_UNUSED_ADDR 0x1000 +#define DUCATI_BOOTVECS_UNUSED_LEN 0x3000 + +#define DUCATI_MEM_CODE_SYSM3_ADDR 0x4000 +#define DUCATI_MEM_CODE_SYSM3_LEN 0x1FC000 + +#define DUCATI_MEM_CODE_APPM3_ADDR 0x800000 +#define DUCATI_MEM_CODE_APPM3_LEN 0x200000 + +#define DUCATI_MEM_CONST_SYSM3_ADDR 0x80000000 +#define DUCATI_MEM_CONST_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_CONST_APPM3_ADDR 0x80100000 +#define DUCATI_MEM_CONST_APPM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_SYSM3_ADDR 0x80200000 +#define DUCATI_MEM_HEAP_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_APPM3_ADDR 0x80300000 +#define DUCATI_MEM_HEAP_APPM3_LEN 0x1000000 + +#define DUCATI_MEM_MPU_DUCATI_SHMEM_ADDR 0x81300000 +#define DUCATI_MEM_MPU_DUCATI_SHMEM_LEN 0xC00000 + +#define DUCATI_MEM_IPC_SHMEM_ADDR 0x81F00000 +#define DUCATI_MEM_IPC_SHMEM_LEN 0x100000 + +#define DUCATI_MEM_IPC_HEAP0_ADDR 0xA0000000 +#define DUCATI_MEM_IPC_HEAP0_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP1_ADDR 0xA0055000 +#define DUCATI_MEM_IPC_HEAP1_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP2_ADDR 0xA00AA000 +#define DUCATI_MEM_IPC_HEAP2_LEN 0x56000 + + +/* Types of mapping attributes */ + +/* MPU address is virtual and needs to be translated to physical addr */ +#define DSP_MAPVIRTUALADDR 0x00000000 +#define DSP_MAPPHYSICALADDR 0x00000001 + +/* Mapped data is big endian */ +#define DSP_MAPBIGENDIAN 0x00000002 +#define DSP_MAPLITTLEENDIAN 0x00000000 + +/* Element size is based on DSP r/w access size */ +#define DSP_MAPMIXEDELEMSIZE 0x00000004 + +/* + * Element size for MMU mapping (8, 16, 32, or 64 bit) + * Ignored if DSP_MAPMIXEDELEMSIZE enabled + */ +#define DSP_MAPELEMSIZE8 0x00000008 +#define DSP_MAPELEMSIZE16 0x00000010 +#define DSP_MAPELEMSIZE32 0x00000020 +#define DSP_MAPELEMSIZE64 0x00000040 + +#define DSP_MAPVMALLOCADDR 0x00000080 +#define DSP_MAPTILERADDR 0x00000100 + + +#define PG_MASK(pg_size) (~((pg_size)-1)) +#define PG_ALIGN_LOW(addr, pg_size) ((addr) & PG_MASK(pg_size)) +#define PG_ALIGN_HIGH(addr, pg_size) (((addr)+(pg_size)-1) & PG_MASK(pg_size)) + + +struct mmu_entry { + u32 ul_phy_addr ; + u32 ul_virt_addr ; + u32 ul_size ; +}; + +struct memory_entry { + u32 ul_virt_addr; + u32 ul_size; +}; + +#if 0 /* Original definitions for OMAP4430. */ +static const struct mmu_entry l4_map[] = { + /* Mailbox 4KB*/ + {L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB}, + /* I2C 4KB each */ + {L4_PERIPHERAL_I2C1, DUCATI_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C2, DUCATI_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C3, DUCATI_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB}, + /* DMA 4KB */ + {L4_PERIPHERAL_DMA, DUCATI_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB}, + /* GPIO Banks 4KB each */ + {L4_PERIPHERAL_GPIO1, DUCATI_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO2, DUCATI_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO3, DUCATI_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB}, + /* GPTimers 4KB each */ + {L4_PERIPHERAL_GPTIMER3, DUCATI_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER4, DUCATI_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11, + HW_PAGE_SIZE_4KB}, + /* UARTs 4KB each */ + {L4_PERIPHERAL_UART1, DUCATI_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART2, DUCATI_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART3, DUCATI_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART4, DUCATI_PERIPHERAL_UART4, + HW_PAGE_SIZE_4KB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* BootVecs regions */ + {0, (PAGE_SIZE_1MB * 2)}, + /* EXTMEM_CORE1: 0x10000000 to 0x100FFFFF */ + {DUCATI_EXTMEM_APPM3_ADDR, DUCATI_EXTMEM_APPM3_LEN}, + /* PRIVATE_SYSM3_DATA*/ + {DUCATI_PRIVATE_SYSM3_DATA_ADDR, DUCATI_PRIVATE_SYSM3_DATA_LEN}, + /* PRIVATE_APPM3_DATA*/ + {DUCATI_PRIVATE_APPM3_DATA_ADDR, DUCATI_PRIVATE_APPM3_DATA_LEN}, + /* SHARED_M3_DATA*/ + {DUCATI_SHARED_M3_DATA_ADDR, DUCATI_SHARED_M3_DATA_LEN}, + /* IPC*/ + {DUCATI_SHARED_IPC_ADDR, DUCATI_SHARED_IPC_LEN}, + /* DMM*/ + {DUCATI_SW_DMM_ADDR, DUCATI_SW_DMM_LEN}, +}; +#endif + +/* OMAP4430 SDC definitions */ +static const struct mmu_entry l4_map[] = { + /* TILER 8-bit and 16-bit modes */ + {L3_TILER_MODE0_1_ADDR, DUCATI_TILER_MODE0_1_ADDR, + (HW_PAGE_SIZE_16MB * 16)}, + /* TILER: Pages-mode */ + {L3_TILER_MODE3_ADDR, DUCATI_TILER_MODE3_ADDR, + (HW_PAGE_SIZE_16MB * 8)}, + /* L4_CFG: Covers all modules in L4_CFG 16MB*/ + {L4_PERIPHERAL_L4CFG, DUCATI_PERIPHERAL_L4CFG, HW_PAGE_SIZE_16MB}, + /* L4_PER: Covers all modules in L4_PER 16MB*/ + {L4_PERIPHERAL_L4PER, DUCATI_PERIPHERAL_L4PER, HW_PAGE_SIZE_16MB}, + /* IVA_HD Config: Covers all modules in IVA_HD Config space 16MB */ + {L3_IVAHD_CONFIG, DUCATI_IVAHD_CONFIG, HW_PAGE_SIZE_16MB}, + /* IVA_HD SL2: Covers all memory in IVA_HD SL2 space 16MB */ + {L3_IVAHD_SL2, DUCATI_IVAHD_SL2, HW_PAGE_SIZE_16MB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* MEM_IPC_HEAP0, MEM_IPC_HEAP1, MEM_IPC_HEAP2 */ + {DUCATI_MEM_IPC_HEAP0_ADDR, PAGE_SIZE_1MB}, + /* MEM_INTVECS_SYSM3, MEM_INTVECS_APPM3, MEM_CODE_SYSM3, + MEM_CODE_APPM3 */ + {0, PAGE_SIZE_16MB}, + /* MEM_CONST_SYSM3, MEM_CONST_APPM3, MEM_HEAP_SYSM3, MEM_HEAP_APPM3, + MEM_MPU_DUCATI_SHMEM, MEM_IPC_SHMEM */ + {DUCATI_MEM_CONST_SYSM3_ADDR, (PAGE_SIZE_16MB * 2)}, +}; + + +void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries); +int ducati_setup(void); +void ducati_destroy(void); +u32 get_ducati_virt_mem(); +void unmap_ducati_virt_mem(u32 shm_virt_addr); +int ducati_mem_map(u32 va, u32 da, u32 num_bytes, u32 map_attr); +int ducati_mem_unmap(u32 da, u32 num_bytes); +u32 user_va2pa(struct mm_struct *mm, u32 address); +inline u32 ducati_mem_virtToPhys(u32 da); +#endif /* _DDUCATIMMU_ENABLER_H_*/ |