diff options
Diffstat (limited to 'arch/arm/plat-omap/include/syslink')
56 files changed, 13149 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/syslink/GlobalTypes.h b/arch/arm/plat-omap/include/syslink/GlobalTypes.h new file mode 100755 index 000000000000..6cd959cde952 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/GlobalTypes.h @@ -0,0 +1,154 @@ +/* + * GlobalTypes.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __GLOBALTYPES_H +#define __GLOBALTYPES_H + +#define REG volatile + +/* + * Definition: RET_CODE_BASE + * + * DESCRIPTION: Base value for return code offsets + * + * + */ +#define RET_CODE_BASE 0 + +/* + * TYPE: ReturnCode_t + * + * DESCRIPTION: Return codes to be returned by all library functions + * + * + */ +enum ReturnCode_label { +RET_OK = 0, +RET_FAIL = -1, +RET_BAD_NULL_PARAM = -2, +RET_PARAM_OUT_OF_RANGE = -3, +RET_INVALID_ID = -4, +RET_EMPTY = -5, +RET_FULL = -6, +RET_TIMEOUT = -7, +RET_INVALID_OPERATION = -8, +/* Add new error codes at end of above list */ +RET_NUM_RET_CODES /* this should ALWAYS be LAST entry */ +}; + + + +/* + * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE + * + * DESCRIPTION: 32 bit register access macros + * + * + */ +#define RD_MEM_32_VOLATILE(addr) \ +((unsigned long)(*((REG unsigned long *)(addr)))) + +#define WR_MEM_32_VOLATILE(addr, data) \ +(*((REG unsigned long *)(addr)) = (unsigned long)(data)) + + + + +#ifdef CHECK_INPUT_PARAMS +/* + * MACRO: CHECK_INPUT_PARAMS + * + * DESCRIPTION: Checks an input code and returns a specified value if code is + * invalid value, also writes spy value if error found. + * + * NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_PARAM(actualValue, invalidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if ((invalidValue) == (actualValue)) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +/* + * MACRO: CHECK_INPUT_RANGE + * + * DESCRIPTION: Checks an input value and returns a specified value if not in + * specified range, also writes spy value if error found. + * +* NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if (((actualValue) < (minValidValue)) || \ + ((actualValue) > (maxValidValue))) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +/* + * MACRO: CHECK_INPUT_RANGE_MIN0 + * + * DESCRIPTION: Checks an input value and returns a + * specified value if not in + * specified range, also writes spy value if error found. + * The minimum + * value is 0. + * + * NOTE: Can be disabled to save HW cycles. + * + * + */ +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) do {\ + if ((actualValue) > (maxValidValue)) {\ + RES_Set((spyCodeIfMisMatch));\ + return returnCodeIfMismatch; \ + } \ +} while (0) + +#else + +#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\ +spyCodeIfMisMatch) + +#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue, \ +returnCodeIfMismatch) + +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) + +#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue , \ +maxValidValue, returnCodeIfMismatch) + +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue, \ +returnCodeIfMismatch, spyCodeIfMisMatch) + +#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, \ +maxValidValue, returnCodeIfMismatch) + +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __GLOBALTYPES_H */ diff --git a/arch/arm/plat-omap/include/syslink/MBXAccInt.h b/arch/arm/plat-omap/include/syslink/MBXAccInt.h new file mode 100755 index 000000000000..84e333d0d5da --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MBXAccInt.h @@ -0,0 +1,550 @@ +/* + * MBXAccInt.h + * + * Notify mailbox driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef _MLB_ACC_INT_H +#define _MLB_ACC_INT_H + + +/* + * EXPORTED DEFINITIONS + * + */ + + +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (unsigned long)(0x0040) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative +to register set MAILBOX_MESSAGE___REGSET_0_15 */ + +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x0080) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative to +register set MAILBOX_FIFOSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (unsigned long)(0x00c0) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (unsigned long)(0x0004) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_BANKS (unsigned long)(16) + +/* Register offset address definitions relative to +register set MAILBOX_MSGSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (unsigned long)(0x0) + + +/*Register set MAILBOX_IRQSTATUS___REGSET_0_3 address +offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (unsigned long)(0x0100) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (unsigned long)(0x0008) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET (unsigned long)(0x0104) +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_BANKS (unsigned long)(4) + +/* Register offset address definitions relative to +register set MAILBOX_IRQSTATUS___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (unsigned long)(0x0) + + +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 +address offset, bank address increment and number of banks */ + +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (unsigned long)(0x0104) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (unsigned long)(0x0008) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET (unsigned long)(0x0108) +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_BANKS (unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET (unsigned long)(0x010C) +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP (unsigned long)(0x0010) +#define MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_BANKS (unsigned long)(4) + +/* Register offset address definitions relative to register +set MAILBOX_IRQENABLE___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (unsigned long)(0x0) + + +/* Register offset address definitions */ + +#define MLB_MAILBOX_REVISION_OFFSET (unsigned long)(0x0) +#define MLB_MAILBOX_SYSCONFIG_OFFSET (unsigned long)(0x10) +#define MLB_MAILBOX_SYSSTATUS_OFFSET (unsigned long)(0x14) + + +/* Bitfield mask and offset declarations */ + +#define MLB_MAILBOX_REVISION_Rev_MASK (unsigned long)(0xff) +#define MLB_MAILBOX_REVISION_Rev_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK (unsigned long)(0x100) +#define MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET (unsigned long)(8) + +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (unsigned long)(0x18) +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (unsigned long)(3) + +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (unsigned long)(0x2) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (unsigned long)(1) + +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK \ +(unsigned long)(0xffffffff) + +#define MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (unsigned long)(0x1) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (unsigned long)(0x7f) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (unsigned long)(0) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK \ +(unsigned long)(0x80000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET \ +(unsigned long)(31) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK \ +(unsigned long)(0x40000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET \ +(unsigned long)(30) + + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK \ +(unsigned long)(0x20000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET \ +(unsigned long)(29) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK \ +(unsigned long)(0x10000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET \ +(unsigned long)(28) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK \ +(unsigned long)(0x8000000) +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET \ +(unsigned long)(27) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK \ +(unsigned long)(0x4000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET \ +(unsigned long)(26) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK \ +(unsigned long)(0x2000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET \ +(unsigned long)(25) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK \ +(unsigned long)(0x1000000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET \ +(unsigned long)(24) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK \ +(unsigned long)(0x800000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET \ +(unsigned long)(23) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK \ +(unsigned long)(0x400000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET \ +(unsigned long)(22) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK \ +(unsigned long)(0x200000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET \ +(unsigned long)(21) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK \ +(unsigned long)(0x100000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET \ +(unsigned long)(20) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK \ +(unsigned long)(0x80000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET \ +(unsigned long)(19) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK \ +(unsigned long)(0x40000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET \ +(unsigned long)(18) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK \ +(unsigned long)(0x20000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET \ +(unsigned long)(17) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK \ +(unsigned long)(0x10000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET \ +(unsigned long)(16) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK \ +(unsigned long)(0x8000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET \ +(unsigned long)(15) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK \ +(unsigned long)(0x4000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET \ +(unsigned long)(14) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK \ +(unsigned long)(0x2000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET \ +(unsigned long)(13) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK \ +(unsigned long)(0x1000) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET \ +(unsigned long)(12) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK \ +(unsigned long)(0x800) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET \ +(unsigned long)(11) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK \ +(unsigned long)(0x400) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET \ +(unsigned long)(10) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK \ +(unsigned long)(0x200) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET \ +(unsigned long)(9) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK \ +(unsigned long)(0x100) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET \ +(unsigned long)(8) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK \ +(unsigned long)(0x80) +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET \ +(unsigned long)(7) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK \ +(unsigned long)(0x40) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET \ +(unsigned long)(6) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK \ +(unsigned long)(0x20) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET \ +(unsigned long)(5) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK \ +(unsigned long)(0x10) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET \ +(unsigned long)(4) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK \ +(unsigned long)(0x8) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET \ +(unsigned long)(3) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK \ +(unsigned long)(0x4) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET \ +(unsigned long)(2) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK \ +(unsigned long)(0x2) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET \ +(unsigned long)(1) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK \ +(unsigned long)(0x1) + +#define MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET \ +(unsigned long)(0) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK \ +(unsigned long)(0x80000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET \ +(unsigned long)(31) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK \ +(unsigned long)(0x40000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET \ +(unsigned long)(30) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK \ +(unsigned long)(0x20000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET \ +(unsigned long)(29) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK \ +(unsigned long)(0x10000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET \ +(unsigned long)(28) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK \ +(unsigned long)(0x8000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET \ +(unsigned long)(27) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK \ +(unsigned long)(0x4000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET \ +(unsigned long)(26) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK \ +(unsigned long)(0x2000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET \ +(unsigned long)(25) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK \ +(unsigned long)(0x1000000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET \ +(unsigned long)(24) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK \ +(unsigned long)(0x800000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET \ +(unsigned long)(23) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK \ +(unsigned long)(0x400000) +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET \ +(unsigned long)(22) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK \ +(unsigned long)(0x200000) +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET \ +(unsigned long)(21) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK \ +(unsigned long)(0x100000) +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET \ +(unsigned long)(20) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK \ +(unsigned long)(0x80000) +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET \ +(unsigned long)(19) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK \ +(unsigned long)(0x40000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET \ +(unsigned long)(18) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK \ +(unsigned long)(0x20000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET \ +(unsigned long)(17) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK \ +(unsigned long)(0x10000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET \ +(unsigned long)(16) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK \ +(unsigned long)(0x8000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET \ +(unsigned long)(15) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK \ +(unsigned long)(0x4000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET \ +(unsigned long)(14) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK \ +(unsigned long)(0x2000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET \ +(unsigned long)(13) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK \ +(unsigned long)(0x1000) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET \ +(unsigned long)(12) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK \ +(unsigned long)(0x800) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET \ +(unsigned long)(11) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK \ +(unsigned long)(0x400) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET \ +(unsigned long)(10) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK \ +(unsigned long)(0x200) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET \ +(unsigned long)(9) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK \ +(unsigned long)(0x100) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET \ +(unsigned long)(8) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK \ +(unsigned long)(0x80) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET \ +(unsigned long)(7) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK \ +(unsigned long)(0x40) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET \ +(unsigned long)(6) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK \ +(unsigned long)(0x20) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET \ +(unsigned long)(5) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK \ +(unsigned long)(0x10) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET \ +(unsigned long)(4) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK \ +(unsigned long)(0x8) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET \ +(unsigned long)(3) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK \ +(unsigned long)(0x4) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET \ +(unsigned long)(2) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK \ +(unsigned long)(0x2) + +#define MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET \ +(unsigned long)(1) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK \ +(unsigned long)(0x1) + +#define MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET \ +(unsigned long)(0) + + +/* + * EXPORTED TYPES + * + */ + +/* The following type definitions +represent the enumerated values for each bitfield */ + +enum MLBMAILBOX_SYSCONFIGSIdleModeE { + MLBMAILBOX_SYSCONFIGSIdleModeb00 = 0x0000, + MLBMAILBOX_SYSCONFIGSIdleModeb01 = 0x0001, + MLBMAILBOX_SYSCONFIGSIdleModeb10 = 0x0002, + MLBMAILBOX_SYSCONFIGSIdleModeb11 = 0x0003 +}; + +enum MLBMAILBOX_SYSCONFIGSoftResetE { + MLBMAILBOX_SYSCONFIGSoftResetb0 = 0x0000, + MLBMAILBOX_SYSCONFIGSoftResetb1 = 0x0001 +}; + +enum MLBMAILBOX_SYSCONFIGAutoIdleE { + MLBMAILBOX_SYSCONFIGAutoIdleb0 = 0x0000, + MLBMAILBOX_SYSCONFIGAutoIdleb1 = 0x0001 +}; + +enum MLBMAILBOX_SYSSTATUSResetDoneE { + MLBMAILBOX_SYSSTATUSResetDonerstongoing = 0x0000, + MLBMAILBOX_SYSSTATUSResetDonerstcomp = 0x0001 +}; + +#endif /* _MLB_ACC_INT_H */ diff --git a/arch/arm/plat-omap/include/syslink/MBXRegAcM.h b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h new file mode 100755 index 000000000000..1c6732ecc9a2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MBXRegAcM.h @@ -0,0 +1,3027 @@ +/* + * MBXRegAcM.h + * + * Notify mailbox driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MBX_REG_ACM_H +#define _MBX_REG_ACM_H + + +#include <syslink/GlobalTypes.h> +#include <syslink/MBXAccInt.h> + + +/* + * EXPORTED DEFINITIONS + * + */ + +#if defined(USE_LEVEL_1_MACROS) + +#define MLBMAILBOX_REVISIONReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_REVISION_OFFSET)) + + + +#define MLBMAILBOX_REVISIONRevRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+ \ +(MLB_MAILBOX_REVISION_OFFSET)))) &\ +MLB_MAILBOX_REVISION_Rev_MASK) >>\ +MLB_MAILBOX_REVISION_Rev_OFFSET)) + + + +#define MLBMAILBOX_REVISIONRevGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_REVISION_Rev_MASK) \ +>> MLB_MAILBOX_REVISION_Rev_OFFSET)) + + + +#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_SYSCONFIG_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \ + offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGClockActivityRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGClockActivityGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_ClockActivity_MASK) \ +>> MLB_MAILBOX_SYSCONFIG_ClockActivity_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0032(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb00 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb0132(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1032(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeReadIsb1132(base_address)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >> \ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0032(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb00 == \ +(MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb0132(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb01 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1032(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb10 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeIsb1132(var)\ +((MLBMAILBOX_SYSCONFIGSIdleModeb11 == (MLBMAILBOX_SYSCONFIGSIdleModeE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+ \ + offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb00 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb0132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb01 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb10 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeWriteb1132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSIdleModeb11 <<\ + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSIdleModeSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK))) + +#define MLBMAILBOX_SYSCONFIGSoftResetRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb032(base_address)\ +((MLBMAILBOX_SYSCONFIGSoftResetb0 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetReadIsb132(base_address)\ +((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >> \ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGSoftResetIsb032(var)\ +((MLBMAILBOX_SYSCONFIGSoftResetb0 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetIsb132(var)\ +((MLBMAILBOX_SYSCONFIGSoftResetb1 == (MLBMAILBOX_SYSCONFIGSoftResetE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_SoftReset_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetWriteb032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb0 <<\ + MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetWriteb132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGSoftResetb1 <<\ + MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGSoftResetSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_SoftReset_MASK))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb032(base_address)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleReadIsb132(base_address)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >> MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + +#define MLBMAILBOX_SYSCONFIGAutoIdleIsb032(var)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb0 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleIsb132(var)\ +((MLBMAILBOX_SYSCONFIGAutoIdleb1 == (MLBMAILBOX_SYSCONFIGAutoIdleE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb032(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb0 <<\ + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleWriteb132(base_address)\ +do {\ + const unsigned long offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + const unsigned long newValue = \ + (unsigned long)MLBMAILBOX_SYSCONFIGAutoIdleb1 <<\ + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + register unsigned long data = \ + RD_MEM_32_VOLATILE((unsigned long)(base_address)+offset);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, data);\ +} while (0) + +#define MLBMAILBOX_SYSCONFIGAutoIdleSet32(var, value)\ +(((((unsigned long)(var)) & ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK)) |\ +((((unsigned long)(value)) << MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK))) + +#define MLBMAILBOX_SYSSTATUSReadRegister32(base_address)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +MLB_MAILBOX_SYSSTATUS_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\ +((((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstongoing32(base_address)\ +((MLBMAILBOX_SYSSTATUSResetDonerstongoing == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneReadisrstcomp32(base_address)\ +((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +(((RD_MEM_32_VOLATILE((((unsigned long)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >> \ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + +#define MLBMAILBOX_SYSSTATUSResetDoneisrstongoing32(var)\ +((MLBMAILBOX_SYSSTATUSResetDonerstongoing == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_SYSSTATUSResetDoneisrstcomp32(var)\ +((MLBMAILBOX_SYSSTATUSResetDonerstcomp == (MLBMAILBOX_SYSSTATUSResetDoneE)\ +((((unsigned long)(var)) & MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))) + +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >>\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET)) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK) >> \ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET)) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmWrite32\ +(base_address, bank, value) do {\ + const unsigned long offset = \ + MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank) * MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK);\ + newValue <<= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET;\ + newValue &= MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_MESSAGE___0_15MessageValueMBmSet32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_OFFSET) &\ +MLB_MAILBOX_MESSAGE___0_15_MessageValueMBm_MASK))) + +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >> \ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + +#define MLBMAILBOX_MSGSTATUS___0_15ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+((bank)*\ +MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmGet32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) \ +>> MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQSTATUS_CLR___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP)))) + +#else + +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) + +#endif + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQSTATUS_CLR___0_3WriteRegister32\ +(base_address, bank, value) do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQSTATUS_CLR___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+ \ + offset, newValue);\ +} while (0) + +#else + +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#endif + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB15Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB15_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB15Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB15_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB14Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB14_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB14Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB14_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB13Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB13_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB13Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB13_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB12Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB12_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB12Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB12_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB11Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB11_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB11Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB11_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB10Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB10_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB10Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB10_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB9Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB9_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB9Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB9_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB8_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB8_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB7Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB7_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB7Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB7_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB6Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB6_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB6Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB6_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Write32\ +(base_address, bank, value)\ +do {\ + onst unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB5Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB5_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB5Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB5_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB4Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB4_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB4Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB4_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB3_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB3_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB2_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK) \ +>> MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB2_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = RD_\ + MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB1Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB1_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB1Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB1_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NotFullStatusUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NotFullStatusUuMB0_MASK))) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >>\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK) >> \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQSTATUS___0_3NewMsgStatusUuMB0Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQSTATUS___0_3_NewMsgStatusUuMB0_MASK))) + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQENABLE_SET___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP)))) + +#else + +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\ +(RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) + +#endif + +#if defined(OMAP44XX) || defined(VPOM4430_1_06) + +#define MLBMAILBOX_IRQENABLE_SET___0_3WriteRegister32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQENABLE_SET___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE_CLR___0_3WriteRegister32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * \ + MLB_MAILBOX_IRQENABLE_CLR___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#else + +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long newValue = ((unsigned long)(value));\ + WR_MEM_32_VOLATILE(((unsigned long)(base_address))+offset, newValue);\ +} while (0) + +#endif + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB15Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB15_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB15Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB15_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB14Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB14_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB14Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB14_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB13Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB13_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB13Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB13_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB12Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB12_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB12Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB12_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB11Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB11_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB11Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB11_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = \ + ((unsigned long)(value));\ + data &= \ + ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK);\ + newValue <<= \ + MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET;\ + newValue \ + &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB10Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB10_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = \ + ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB10Set32\ +(var, value)\ +(((((unsigned long)(var)) &\ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB10_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB9Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB9_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB9Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB9_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB8Set32(var, value)\ +(((((unsigned long)(var)) & \ +~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB8_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB8Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB8_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB7Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB7_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Get32(var)\ +((unsigned long)((((unsigned long)(var)) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB7Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB7_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB6Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB6_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB6Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB6_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Read32(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB5Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB5_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB5Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB5_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Get32\ +(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB4Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB4_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB4Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB4_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Get32\ +(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB3Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB3_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB3Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB3_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB2Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB2_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB2Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB2_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))\ ++(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)\ +*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) \ +& MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB1Set32\ +(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK)) |\ +((((unsigned long)(value)) << \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB1_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Read32\ +(base_address, bank) do {\ + ((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ + (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ + MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >>\ + MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET))\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK) >> \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB1Set32(var, value)\ +(((((unsigned long)(var)) &\ +~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB1_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NotFullEnableUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NotFullEnableUuMB0_MASK))) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Read32\ +(base_address, bank)\ +((((RD_MEM_32_VOLATILE(((unsigned long)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+((bank)*\ +MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) >>\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Get32(var)\ +((unsigned long)((((unsigned long)(var)) & \ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK) \ +>> MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET)) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Write32\ +(base_address, bank, value)\ +do {\ + const unsigned long offset = \ + MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank) * MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register unsigned long data = \ + RD_MEM_32_VOLATILE(((unsigned long)(base_address))+offset);\ + register unsigned long newValue = ((unsigned long)(value));\ + data &= ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK);\ + newValue <<= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET;\ + newValue &= MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((unsigned long)(base_address)+offset, newValue);\ +} while (0) + +#define MLBMAILBOX_IRQENABLE___0_3NewMsgEnableUuMB0Set32(var, value)\ +(((((unsigned long)(var)) \ +& ~(MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK)) |\ +((((unsigned long)(value)) \ +<< MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_OFFSET) &\ +MLB_MAILBOX_IRQENABLE___0_3_NewMsgEnableUuMB0_MASK))) + +#endif /* USE_LEVEL_1_MACROS */ + + +#endif /* _MBX_REG_ACM_H */ diff --git a/arch/arm/plat-omap/include/syslink/MLBAccInt.h b/arch/arm/plat-omap/include/syslink/MLBAccInt.h new file mode 100755 index 000000000000..6cd469709005 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MLBAccInt.h @@ -0,0 +1,132 @@ +/* + * MLBAccInt.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef _MLB_ACC_INT_H +#define _MLB_ACC_INT_H + +/* Mappings of level 1 EASI function numbers to function names */ + +#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32 (MLB_BASE_EASIL1 + 3) +#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32 (MLB_BASE_EASIL1 + 4) +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32 (MLB_BASE_EASIL1 + 7) +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32 (MLB_BASE_EASIL1 + 17) +#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29) +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \ + (MLB_BASE_EASIL1 + 33) +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32 (MLB_BASE_EASIL1 + 39) +#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32 (MLB_BASE_EASIL1 + 44) +#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \ + (MLB_BASE_EASIL1 + 50) +#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32 \ + (MLB_BASE_EASIL1 + 51) +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32 \ + (MLB_BASE_EASIL1 + 56) +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \ + (MLB_BASE_EASIL1 + 57) +#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32 \ + (MLB_BASE_EASIL1 + 60) +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32 \ + (MLB_BASE_EASIL1 + 62) +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \ + (MLB_BASE_EASIL1 + 63) +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32 \ + (MLB_BASE_EASIL1 + 192) +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32 \ + (MLB_BASE_EASIL1 + 193) + +/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (u32)(0x0040) +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_MESSAGE___REGSET_0_15 */ + +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (u32)(0x0080) +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_FIFOSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (u32)(0x00c0) +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (u32)(0x0004) + +/* Register offset address definitions relative to register set + * MAILBOX_MSGSTATUS___REGSET_0_15 */ + +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (u32)(0x0100) +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (u32)(0x0008) + +/* Register offset address definitions relative to register set + * MAILBOX_IRQSTATUS___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (u32)(0x0) + + +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address + * increment and number of banks */ + +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (u32)(0x0104) +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (u32)(0x0008) + +/* Register offset address definitions relative to register set + * MAILBOX_IRQENABLE___REGSET_0_3 */ + +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (u32)(0x0) + + +/* Register offset address definitions */ + +#define MLB_MAILBOX_SYSCONFIG_OFFSET (u32)(0x10) +#define MLB_MAILBOX_SYSSTATUS_OFFSET (u32)(0x14) + + +/* Bitfield mask and offset declarations */ + +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (u32)(0x18) +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (u32)(3) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (u32)(0x2) +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (u32)(1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (u32)(0x1) +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (u32)(0) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (u32)(0x1) +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (u32)(0) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (u32)(0x1) +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (u32)(0) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (u32)(0x7f) +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (u32)(0) + +#endif /* _MLB_ACC_INT_H */ diff --git a/arch/arm/plat-omap/include/syslink/MLBRegAcM.h b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h new file mode 100755 index 000000000000..5ef9cf32aef2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MLBRegAcM.h @@ -0,0 +1,206 @@ +/* + * MLBRegAcM.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2007 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MLB_REG_ACM_H +#define _MLB_REG_ACM_H + +#include <syslink/GlobalTypes.h> +#include <syslink/EasiGlobal.h> +#include <syslink/MLBAccInt.h> + +#if defined(USE_LEVEL_1_MACROS) + +#define MLBMAILBOX_SYSCONFIGReadRegister32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+ \ +MLB_MAILBOX_SYSCONFIG_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGWriteRegister32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(((u32)(base_address)) +\ + offset);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(base_address, value)\ +do {\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data =\ + RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\ + register u32 newValue = ((u32)(value));\ + printk(KERN_ALERT "In SYSCONFIG MACOR line %i file %s", \ + __LINE__, __FILE__);\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\ + printk(KERN_ALERT "******************BEFORE DATA WRITE");\ + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\ + newValue |= data;\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ + printk(KERN_ALERT "line %i file %s", __LINE__, __FILE__);\ +} while (0) + + +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\ +MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET)) + + +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(base_address, value)\ +{\ + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\ + register u32 data =\ + RD_MEM_32_VOLATILE(((u32)(base_address))+offset);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\ + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\ + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\ + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE((u32)(base_address)+offset, newValue);\ +} + + +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(base_address)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\ +(((RD_MEM_32_VOLATILE((((u32)(base_address))+\ +(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\ +MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\ +MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET)) + + +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\ +(bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP)))) + + +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\ + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\ + ((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) + + +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\ +(((RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\ +MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET)) + + +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(\ +EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\ +(((RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\ +MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\ +((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\ +MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET)) + + +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP)))) + + +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\ + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(base_address, bank)\ +(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\ +RD_MEM_32_VOLATILE(((u32)(base_address))+\ +(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ +MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\ +((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP)))) + + +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(base_address, bank, value)\ +do {\ + const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\ + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\ + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\ + register u32 newValue = ((u32)(value));\ + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\ + WR_MEM_32_VOLATILE(((u32)(base_address))+offset, newValue);\ +} while (0) + + +#endif /* USE_LEVEL_1_MACROS */ + +#endif /* _MLB_REG_ACM_H */ diff --git a/arch/arm/plat-omap/include/syslink/MMUAccInt.h b/arch/arm/plat-omap/include/syslink/MMUAccInt.h new file mode 100755 index 000000000000..827e1bc16b62 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MMUAccInt.h @@ -0,0 +1,179 @@ +/* + * MMUAccInt.h + * + * Syslink ducati driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MMU_ACC_INT_H +#define _MMU_ACC_INT_H + + +/* Register offset address definitions */ + +#define MMU_MMU_REVISION_OFFSET 0x0 +#define MMU_MMU_SYSCONFIG_OFFSET 0x10 +#define MMU_MMU_SYSSTATUS_OFFSET 014 +#define MMU_MMU_IRQSTATUS_OFFSET 0x18 +#define MMU_MMU_IRQENABLE_OFFSET 0x1c +#define MMU_MMU_WALKING_ST_OFFSET 0x40 +#define MMU_MMU_CNTL_OFFSET 0x44 +#define MMU_MMU_FAULT_AD_OFFSET 0x48 +#define MMU_MMU_TTB_OFFSET 0x4c +#define MMU_MMU_LOCK_OFFSET 0x50 +#define MMU_MMU_LD_TLB_OFFSET 0x54 +#define MMU_MMU_CAM_OFFSET 0x58 +#define MMU_MMU_RAM_OFFSET 0x5c +#define MMU_MMU_GFLUSH_OFFSET 0x60 +#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64 +#define MMU_MMU_READ_CAM_OFFSET 0x68 +#define MMU_MMU_READ_RAM_OFFSET 0x6c +#define MMU_MMU_EMU_FAULT_AD_OFFSET 0x70 + + +/* Bitfield mask and offset declarations */ + +#define MMU_MMU_REVISION_Rev_MASK 0xff +#define MMU_MMU_REVISION_Rev_OFFSET 0 + +#define MMU_MMU_SYSCONFIG_ClockActivity_MASK 0x300 +#define MMU_MMU_SYSCONFIG_ClockActivity_OFFSET 8 + +#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18 +#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3 + +#define MMU_MMU_SYSCONFIG_SoftReset_MASK 0x2 +#define MMU_MMU_SYSCONFIG_SoftReset_OFFSET 1 + +#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1 +#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0 + +#define MMU_MMU_SYSSTATUS_ResetDone_MASK 0x1 +#define MMU_MMU_SYSSTATUS_ResetDone_OFFSET 0 + +#define MMU_MMU_IRQSTATUS_MultiHitFault_MASK 0x10 +#define MMU_MMU_IRQSTATUS_MultiHitFault_OFFSET 4 + +#define MMU_MMU_IRQSTATUS_TableWalkFault_MASK 0x8 +#define MMU_MMU_IRQSTATUS_TableWalkFault_OFFSET 3 + +#define MMU_MMU_IRQSTATUS_EMUMiss_MASK 0x4 +#define MMU_MMU_IRQSTATUS_EMUMiss_OFFSET 2 + +#define MMU_MMU_IRQSTATUS_TranslationFault_MASK 0x2 +#define MMU_MMU_IRQSTATUS_TranslationFault_OFFSET 1 + +#define MMU_MMU_IRQSTATUS_TLBMiss_MASK 0x1 +#define MMU_MMU_IRQSTATUS_TLBMiss_OFFSET 0 + +#define MMU_MMU_IRQENABLE_MultiHitFault_MASK 0x10 +#define MMU_MMU_IRQENABLE_MultiHitFault_OFFSET 4 + +#define MMU_MMU_IRQENABLE_TableWalkFault_MASK 0x8 +#define MMU_MMU_IRQENABLE_TableWalkFault_OFFSET 3 + +#define MMU_MMU_IRQENABLE_EMUMiss_MASK 0x4 +#define MMU_MMU_IRQENABLE_EMUMiss_OFFSET 2 + +#define MMU_MMU_IRQENABLE_TranslationFault_MASK 0x2 +#define MMU_MMU_IRQENABLE_TranslationFault_OFFSET 1 + +#define MMU_MMU_IRQENABLE_TLBMiss_MASK 0x1 +#define MMU_MMU_IRQENABLE_TLBMiss_OFFSET 0 + +#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1 +#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0 + +#define MMU_MMU_CNTL_EmuTLBUpdate_MASK 0x8 +#define MMU_MMU_CNTL_EmuTLBUpdate_OFFSET 3 + +#define MMU_MMU_CNTL_TWLEnable_MASK 0x4 +#define MMU_MMU_CNTL_TWLEnable_OFFSET 2 + +#define MMU_MMU_CNTL_MMUEnable_MASK 0x2 +#define MMU_MMU_CNTL_MMUEnable_OFFSET 1 + +#define MMU_MMU_FAULT_AD_FaultAddress_MASK 0xffffffff +#define MMU_MMU_FAULT_AD_FaultAddress_OFFSET 0 + +#define MMU_MMU_TTB_TTBAddress_MASK 0xffffff00 +#define MMU_MMU_TTB_TTBAddress_OFFSET 8 + +#define MMU_MMU_LOCK_BaseValue_MASK 0xfc00 +#define MMU_MMU_LOCK_BaseValue_OFFSET 10 + +#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0 +#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4 + +#define MMU_MMU_LD_TLB_LdTLBItem_MASK 0x1 +#define MMU_MMU_LD_TLB_LdTLBItem_OFFSET 0 + +#define MMU_MMU_CAM_VATag_MASK 0xfffff000 +#define MMU_MMU_CAM_VATag_OFFSET 12 + +#define MMU_MMU_CAM_P_MASK 0x8 +#define MMU_MMU_CAM_P_OFFSET 3 + +#define MMU_MMU_CAM_V_MASK 0x4 +#define MMU_MMU_CAM_V_OFFSET 2 + +#define MMU_MMU_CAM_PageSize_MASK 0x3 +#define MMU_MMU_CAM_PageSize_OFFSET 0 + +#define MMU_MMU_RAM_PhysicalAddress_MASK 0xfffff000 +#define MMU_MMU_RAM_PhysicalAddress_OFFSET 12 + +#define MMU_MMU_RAM_Endianness_MASK 0x200 +#define MMU_MMU_RAM_Endianness_OFFSET 9 + +#define MMU_MMU_RAM_ElementSize_MASK 0x180 +#define MMU_MMU_RAM_ElementSize_OFFSET 7 + +#define MMU_MMU_RAM_Mixed_MASK 0x40 +#define MMU_MMU_RAM_Mixed_OFFSET 6 + +#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1 +#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0 + +#define MMU_MMU_FLUSH_ENTRY_FlushEntry_MASK 0x1 +#define MMU_MMU_FLUSH_ENTRY_FlushEntry_OFFSET 0 + +#define MMU_MMU_READ_CAM_VATag_MASK 0xfffff000 +#define MMU_MMU_READ_CAM_VATag_OFFSET 12 + +#define MMU_MMU_READ_CAM_P_MASK 0x8 +#define MMU_MMU_READ_CAM_P_OFFSET 3 + +#define MMU_MMU_READ_CAM_V_MASK 0x4 +#define MMU_MMU_READ_CAM_V_OFFSET 2 + +#define MMU_MMU_READ_CAM_PageSize_MASK 0x3 +#define MMU_MMU_READ_CAM_PageSize_OFFSET 0 + +#define MMU_MMU_READ_RAM_PhysicalAddress_MASK 0xfffff000 +#define MMU_MMU_READ_RAM_PhysicalAddress_OFFSET 12 + +#define MMU_MMU_READ_RAM_Endianness_MASK 0x200 +#define MMU_MMU_READ_RAM_Endianness_OFFSET 9 + +#define MMU_MMU_READ_RAM_ElementSize_MASK 0x180 +#define MMU_MMU_READ_RAM_ElementSize_OFFSET 7 + +#define MMU_MMU_READ_RAM_Mixed_MASK 0x40 +#define MMU_MMU_READ_RAM_Mixed_OFFSET 6 + +#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_MASK 0xffffffff +#define MMU_MMU_EMU_FAULT_AD_EmuFaultAddress_OFFSET 0 + +#endif /* _MMU_ACC_INT_H */ +/* EOF */ + diff --git a/arch/arm/plat-omap/include/syslink/MMURegAcM.h b/arch/arm/plat-omap/include/syslink/MMURegAcM.h new file mode 100755 index 000000000000..8088ca94f9c2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/MMURegAcM.h @@ -0,0 +1,427 @@ +/* + * MMURegAcM.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef _MMU_REG_ACM_H +#define _MMU_REG_ACM_H + + + +#include "GlobalTypes.h" +#include "MMUAccInt.h" + + +/* +* EXPORTED DEFINITIONS +* +*/ + +#if defined(USE_LEVEL_1_MACROS) + + +#define MMUMMU_SYSCONFIGReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_SYSCONFIG_OFFSET)) + + +#define MMUMMU_SYSCONFIGWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_SYSCONFIGClockActivityGet32(var)\ + ((u32)(((var) & MMU_MMU_SYSCONFIG_ClockActivity_MASK)\ + >> MMU_MMU_SYSCONFIG_ClockActivity_OFFSET)) + +#define mmu_sisconf_auto_idle_set32(var, value)\ + ((((var) & ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK)) |\ + (((value) << MMU_MMU_SYSCONFIG_AutoIdle_OFFSET) &\ + MMU_MMU_SYSCONFIG_AutoIdle_MASK))) + +#define MMUMMU_IRQSTATUSReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQSTATUS_OFFSET)) + + +#define MMUMMU_IRQSTATUSWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + + +#define MMUMMU_IRQENABLEReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_IRQENABLE_OFFSET)) + + +#define MMUMMU_IRQENABLEWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_IRQENABLETableWalkFaultSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TableWalkFault_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TableWalkFault_OFFSET) &\ + MMU_MMU_IRQENABLE_TableWalkFault_MASK))) + +#define MMUMMU_IRQENABLETranslationFaultRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TranslationFault_MASK) >>\ + MMU_MMU_IRQENABLE_TranslationFault_OFFSET)) + + + +#define MMUMMU_IRQENABLETranslationFaultSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TranslationFault_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TranslationFault_OFFSET) &\ + MMU_MMU_IRQENABLE_TranslationFault_MASK))) + + +#define MMUMMU_IRQENABLETLBMissRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET)) + + +#define MMUMMU_IRQENABLETLBMissReadIsTrMissIntM32(base_address)\ + ((MMUMMU_IRQENABLETLBMissTrMissIntM == (MMUMMU_IRQENABLETLBMissE)\ + (((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + + +#define MMUMMU_IRQENABLETLBMissReadIsTrMissGInt32(base_address)\ + ((MMUMMU_IRQENABLETLBMissTrMissGInt == (MMUMMU_IRQENABLETLBMissE)\ + (((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_IRQENABLE_OFFSET)))) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + + +#define MMUMMU_IRQENABLETLBMissGet32(var)\ + ((u32)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK)\ + >> MMU_MMU_IRQENABLE_TLBMiss_OFFSET)) + + +#define MMUMMU_IRQENABLETLBMissIsTrMissIntM32(var)\ + ((MMUMMU_IRQENABLETLBMissTrMissIntM == \ + (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + +#define MMUMMU_IRQENABLETLBMissIsTrMissGInt32(var)\ + ((MMUMMU_IRQENABLETLBMissTrMissGInt ==\ + (MMUMMU_IRQENABLETLBMissE)(((var) & MMU_MMU_IRQENABLE_TLBMiss_MASK) >>\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET))) + +#define MMUMMU_IRQENABLETLBMissWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + newValue <<= MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + newValue &= MMU_MMU_IRQENABLE_TLBMiss_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_IRQENABLETLBMissWriteTrMissIntM32(base_address)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissIntM <<\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_IRQENABLETLBMissWriteTrMissGInt32(base_address)\ +{\ + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\ + const u32 newValue = (u32)MMUMMU_IRQENABLETLBMissTrMissGInt <<\ + MMU_MMU_IRQENABLE_TLBMiss_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_IRQENABLE_TLBMiss_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_IRQENABLETLBMissSet32(var, value)\ + ((((var) & ~(MMU_MMU_IRQENABLE_TLBMiss_MASK)) |\ + (((value) << MMU_MMU_IRQENABLE_TLBMiss_OFFSET) &\ + MMU_MMU_IRQENABLE_TLBMiss_MASK))) + + +#define MMUMMU_WALKING_STTWLRunningRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_WALKING_ST_OFFSET)))) &\ + MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\ + MMU_MMU_WALKING_ST_TWLRunning_OFFSET)) + + + +#define MMUMMU_CNTLTWLEnableRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\ + MMU_MMU_CNTL_TWLEnable_MASK) >>\ + MMU_MMU_CNTL_TWLEnable_OFFSET)) + + +#define MMUMMU_CNTLTWLEnableWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CNTL_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\ + newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\ + newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_CNTLMMUEnableWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CNTL_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\ + newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\ + newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_FAULT_ADReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FAULT_AD_OFFSET)) + + +#define MMUMMU_FAULT_ADFaultAddressRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_FAULT_AD_OFFSET)))) &\ + MMU_MMU_FAULT_AD_FaultAddress_MASK) >>\ + MMU_MMU_FAULT_AD_FaultAddress_OFFSET)) + +#define MMUMMU_FAULT_ADFaultAddressGet32(var)\ + ((u32)(((var) & MMU_MMU_FAULT_AD_FaultAddress_MASK)\ + >> MMU_MMU_FAULT_AD_FaultAddress_OFFSET)) + + +#define MMUMMU_TTBReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_TTB_OFFSET)) + +#define MMUMMU_TTBWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_TTB_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_TTBTTBAddressRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_TTB_OFFSET)))) &\ + MMU_MMU_TTB_TTBAddress_MASK) >>\ + MMU_MMU_TTB_TTBAddress_OFFSET)) + +#define MMUMMU_TTBTTBAddressGet32(var)\ + ((u32)(((var) & MMU_MMU_TTB_TTBAddress_MASK)\ + >> MMU_MMU_TTB_TTBAddress_OFFSET)) + + +#define MMUMMU_TTBTTBAddressWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_TTB_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_TTB_TTBAddress_MASK);\ + newValue <<= MMU_MMU_TTB_TTBAddress_OFFSET;\ + newValue &= MMU_MMU_TTB_TTBAddress_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + +#define MMUMMU_TTBTTBAddressSet32(var, value)\ + ((((var) & ~(MMU_MMU_TTB_TTBAddress_MASK)) |\ + (((value) << MMU_MMU_TTB_TTBAddress_OFFSET) &\ + MMU_MMU_TTB_TTBAddress_MASK))) + + +#define mmu_lckread_reg_32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LOCK_OFFSET)) + +#define mmu_lck_write_reg32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + + +#define MMUMMU_LOCKBaseValueRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\ + MMU_MMU_LOCK_BaseValue_MASK) >>\ + MMU_MMU_LOCK_BaseValue_OFFSET)) +#define MMUMMU_LOCKBaseValueGet32(var)\ + ((u32)(((var) & MMU_MMU_LOCK_BaseValue_MASK)\ + >> MMU_MMU_LOCK_BaseValue_OFFSET)) + + +#define MMUMMU_LOCKBaseValueWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\ + newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\ + newValue &= MMU_MMU_LOCK_BaseValue_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_LOCKBaseValueSet32(var, value)\ + ((((var) & ~(MMU_MMU_LOCK_BaseValue_MASK)) |\ + (((value) << MMU_MMU_LOCK_BaseValue_OFFSET) &\ + MMU_MMU_LOCK_BaseValue_MASK))) + +#define MMUMMU_LOCKCurrentVictimRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\ + MMU_MMU_LOCK_CurrentVictim_MASK) >>\ + MMU_MMU_LOCK_CurrentVictim_OFFSET)) + + +#define MMUMMU_LOCKCurrentVictimGet32(var)\ + ((u32)(((var) & MMU_MMU_LOCK_CurrentVictim_MASK)\ + >> MMU_MMU_LOCK_CurrentVictim_OFFSET)) + + +#define mmu_lck_crnt_vctmwite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LOCK_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\ + newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\ + newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + + +#define MMUMMU_LOCKCurrentVictimSet32(var, value)\ + ((((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\ + (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\ + MMU_MMU_LOCK_CurrentVictim_MASK))) + + +#define MMUMMU_LD_TLBReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_LD_TLB_OFFSET)) + +#define mmu_ld_tlbwrt_reg32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_LD_TLB_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_LD_TLBLdTLBItemRead32(base_address)\ + ((((RD_MEM_32_VOLATILE(((base_address)+(MMU_MMU_LD_TLB_OFFSET)))) &\ + MMU_MMU_LD_TLB_LdTLBItem_MASK) >>\ + MMU_MMU_LD_TLB_LdTLBItem_OFFSET)) + + +#define MMUMMU_CAMReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_CAM_OFFSET)) + + +#define MMUMMU_CAMWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_CAM_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_RAMReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_READ_RAM_OFFSET)) + + +#define MMUMMU_RAMWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_RAM_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWrite32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE((base_address)+offset);\ + register u32 newValue = (value);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\ + newValue |= data;\ + WR_MEM_32_VOLATILE(base_address+offset, newValue);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWritenft_w32(base_address)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushnft_w <<\ + MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + +#define MMUMMU_GFLUSHGlobalFlushWriteflush_w32(base_address)\ +{\ + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\ + const u32 newValue = (u32)MMUMMU_GFLUSHGlobalFlushflush_w <<\ + MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\ + register u32 data = RD_MEM_32_VOLATILE(base_address+offset);\ + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\ + data |= newValue;\ + WR_MEM_32_VOLATILE(base_address+offset, data);\ +} + + +#define MMUMMU_GFLUSHGlobalFlushSet32(var, value)\ + ((((var) & ~(MMU_MMU_GFLUSH_GlobalFlush_MASK)) |\ + (((value) << MMU_MMU_GFLUSH_GlobalFlush_OFFSET) &\ + MMU_MMU_GFLUSH_GlobalFlush_MASK))) + +#define MMUMMU_FLUSH_ENTRYReadRegister32(base_address)\ + (RD_MEM_32_VOLATILE((base_address)+MMU_MMU_FLUSH_ENTRY_OFFSET)) + + +#define MMUMMU_FLUSH_ENTRYWriteRegister32(base_address, value)\ +{\ + const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\ + register u32 newValue = (value);\ + WR_MEM_32_VOLATILE((base_address)+offset, newValue);\ +} + + + +#endif /* USE_LEVEL_1_MACROS */ + +#endif /* _MMU_REG_ACM_H */ +/* EOF */ + diff --git a/arch/arm/plat-omap/include/syslink/_sysmgr.h b/arch/arm/plat-omap/include/syslink/_sysmgr.h new file mode 100644 index 000000000000..58fbdd378155 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/_sysmgr.h @@ -0,0 +1,50 @@ +/* + * _sysmgr.h + * + * Defines for system manager functions + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __SYSMGR_H_ +#define __SYSMGR_H_ + +/* Structure to retrieve the scalability proc info from the slave */ +struct sysmgr_proc_config { + u32 proc_id; + u32 use_notify; + u32 use_messageq; + u32 use_heapbuf; + u32 use_frameq; + u32 use_ringio; + u32 use_listmp; + u32 use_nameserver; + u32 boot_mode; +}; + +/* Function to set the boot load page address for a slave */ +void sysmgr_set_boot_load_page(u16 proc_id, u32 boot_load_page); + +/* Function to get configuration values for a host object(component/instance) */ +u32 sysmgr_get_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size); + +/* Function to put configuration values for a slave object(component/instance)*/ +u32 sysmgr_put_object_config(u16 proc_id, void *config, u32 cmd_id, u32 size); + +/* Function to wait for scalability handshake value. */ +void sysmgr_wait_for_scalability_info(u16 proc_id); + +/* Function to wait for slave to complete setup */ +void sysmgr_wait_for_slave_setup(u16 proc_id); + + +#endif /* ifndef __SYSMGR_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/atomic_linux.h b/arch/arm/plat-omap/include/syslink/atomic_linux.h new file mode 100755 index 000000000000..e36cb8ba2abc --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/atomic_linux.h @@ -0,0 +1,105 @@ +/* +* atomic_linux.h +* +* Atomic operations functions +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _ATOMIC_LINUX_H +#define _ATOMIC_LINUX_H + +#include <linux/types.h> +#include <linux/autoconf.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <asm/atomic.h> + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and set if not equal + */ +static inline void atomic_cmpmask_and_set(atomic_t *v, u32 mask, u32 val) +{ + s32 ret; + unsigned long flags; + atomic_t *atm = v; + + raw_local_irq_save(flags); + ret = atm->counter; + if (likely(((ret & mask) != mask))) + atm->counter = val; + raw_local_irq_restore(flags); +} + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and then check current value less than + * provided value. + */ +static inline bool atomic_cmpmask_and_lt(atomic_t *v, u32 mask, u32 val) +{ + bool ret = true; + atomic_t *atm = v; + s32 cur; + unsigned long flags; + + raw_local_irq_save(flags); + cur = atm->counter; + /* Compare mask, if matches then compare val */ + if (likely(((cur & mask) == mask))) { + if (likely(cur >= val)) + ret = false; + } + raw_local_irq_restore(flags); + + /* retval = true if mask matches and current value is less than given + * value */ + /* retval = false either mask doesnot matches or current value is not + * less than given value */ + return ret; +} + + +/* + * ======== atomic_cmpmask_and_set ======== + * Purpose: + * This will compare a mask and then check current value greater than + * provided value. + */ +static inline bool atomic_cmpmask_and_gt(atomic_t *v, u32 mask, u32 val) +{ + bool ret = false; + atomic_t *atm = v; + s32 cur; + unsigned long flags; + + raw_local_irq_save(flags); + cur = atm->counter; + /* Compare mask, if matches then compare val */ + if (likely(((cur & mask) == mask))) { + if (likely(cur > val)) + ret = true; + } + + raw_local_irq_restore(flags); + /* retval = true if mask matches and current value is less than given + * value */ + /* etval =false either mask doesnot matches or current value is not + * greater than given value */ + return ret; +} + +#endif /* if !defined(_ATOMIC_LINUX_H) */ + diff --git a/arch/arm/plat-omap/include/syslink/ducatienabler.h b/arch/arm/plat-omap/include/syslink/ducatienabler.h new file mode 100644 index 000000000000..09212f58738d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ducatienabler.h @@ -0,0 +1,291 @@ +/* + * ducatienabler.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef _DDUCATIMMU_ENABLER_H_ +#define _DDUCATIMMU_ENABLER_H_ + +#include <linux/types.h> +#include <linux/mm.h> + +#include <syslink/hw_defs.h> +#include <syslink/hw_mmu.h> + + +#define PAGE_SIZE_4KB 0x1000 +#define PAGE_SIZE_64KB 0x10000 +#define PAGE_SIZE_1MB 0x100000 +#define PAGE_SIZE_16MB 0x1000000 + +/* Define the Peripheral PAs and their Ducati VAs. */ +#define L4_PERIPHERAL_MBOX 0x4A0F4000 +#define DUCATI_PERIPHERAL_MBOX 0xAA0F4000 + +#define L4_PERIPHERAL_I2C1 0x48070000 +#define DUCATI_PERIPHERAL_I2C1 0xA8070000 +#define L4_PERIPHERAL_I2C2 0x48072000 +#define DUCATI_PERIPHERAL_I2C2 0xA8072000 +#define L4_PERIPHERAL_I2C3 0x48060000 +#define DUCATI_PERIPHERAL_I2C3 0xA8060000 + +#define L4_PERIPHERAL_DMA 0x4A056000 +#define DUCATI_PERIPHERAL_DMA 0xAA056000 + +#define L4_PERIPHERAL_GPIO1 0x4A310000 +#define DUCATI_PERIPHERAL_GPIO1 0xAA310000 +#define L4_PERIPHERAL_GPIO2 0x48055000 +#define DUCATI_PERIPHERAL_GPIO2 0xA8055000 +#define L4_PERIPHERAL_GPIO3 0x48057000 +#define DUCATI_PERIPHERAL_GPIO3 0xA8057000 + +#define L4_PERIPHERAL_GPTIMER3 0x48034000 +#define DUCATI_PERIPHERAL_GPTIMER3 0xA8034000 +#define L4_PERIPHERAL_GPTIMER4 0x48036000 +#define DUCATI_PERIPHERAL_GPTIMER4 0xA8036000 +#define L4_PERIPHERAL_GPTIMER9 0x48040000 +#define DUCATI_PERIPHERAL_GPTIMER9 0xA8040000 +#define L4_PERIPHERAL_GPTIMER11 0x48088000 +#define DUCATI_PERIPHERAL_GPTIMER11 0xA8088000 + +#define L4_PERIPHERAL_UART1 0x4806A000 +#define DUCATI_PERIPHERAL_UART1 0xA806A000 +#define L4_PERIPHERAL_UART2 0x4806C000 +#define DUCATI_PERIPHERAL_UART2 0xA806C000 +#define L4_PERIPHERAL_UART3 0x48020000 +#define DUCATI_PERIPHERAL_UART3 0xA8020000 +#define L4_PERIPHERAL_UART4 0x4806E000 +#define DUCATI_PERIPHERAL_UART4 0xA806E000 + + +#define L3_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_ADDR 0x60000000 +#define DUCATIVA_TILER_VIEW0_LEN 0x20000000 + + + +#if 0 /* Original definitions for OMAP4430. */ +/* Define the various Ducati Memory Regions. */ +/* The first 4K page of BOOTVECS is programmed as a TLB entry. The remaining */ +/* three pages are not used and are mapped to minimize number of PTEs */ +#define DUCATI_BOOTVECS_ADDR 0x1000 +#define DUCATI_BOOTVECS_LEN 0x3000 + +#define DUCATI_EXTMEM_SYSM3_ADDR 0x4000 +#define DUCATI_EXTMEM_SYSM3_LEN 0x1FC000 + +#define DUCATI_EXTMEM_APPM3_ADDR 0x10000000 +#define DUCATI_EXTMEM_APPM3_LEN 0x200000 + +#define DUCATI_PRIVATE_SYSM3_DATA_ADDR 0x84000000 +#define DUCATI_PRIVATE_SYSM3_DATA_LEN 0x200000 + +#define DUCATI_PRIVATE_APPM3_DATA_ADDR 0x8A000000 +#define DUCATI_PRIVATE_APPM3_DATA_LEN 0x200000 + +#define DUCATI_SHARED_M3_DATA_ADDR 0x90000000 +#define DUCATI_SHARED_M3_DATA_LEN 0x100000 + +#define DUCATI_SHARED_IPC_ADDR 0x98000000 +#define DUCATI_SHARED_IPC_LEN 0x100000 + +#define DUCATI_SW_DMM_ADDR 0x80000000 +#define DUCATI_SW_DMM_LEN 0x400000 +#endif + +/* OMAP4430 SDC definitions */ +#define L4_PERIPHERAL_L4CFG 0x4A000000 +#define DUCATI_PERIPHERAL_L4CFG 0xAA000000 + +#define L4_PERIPHERAL_L4PER 0x48000000 +#define DUCATI_PERIPHERAL_L4PER 0xA8000000 + +#define L3_IVAHD_CONFIG 0x5A000000 +#define DUCATI_IVAHD_CONFIG 0xBA000000 + +#define L3_IVAHD_SL2 0x5B000000 +#define DUCATI_IVAHD_SL2 0xBB000000 + +#define L3_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_ADDR 0x60000000 +#define DUCATI_TILER_MODE0_1_LEN 0x10000000 + +#define L3_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_ADDR 0x78000000 +#define DUCATI_TILER_MODE3_LEN 0x8000000 + +#define DUCATI_BOOTVECS_UNUSED_ADDR 0x1000 +#define DUCATI_BOOTVECS_UNUSED_LEN 0x3000 + +#define DUCATI_MEM_CODE_SYSM3_ADDR 0x4000 +#define DUCATI_MEM_CODE_SYSM3_LEN 0x1FC000 + +#define DUCATI_MEM_CODE_APPM3_ADDR 0x800000 +#define DUCATI_MEM_CODE_APPM3_LEN 0x200000 + +#define DUCATI_MEM_CONST_SYSM3_ADDR 0x80000000 +#define DUCATI_MEM_CONST_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_CONST_APPM3_ADDR 0x80100000 +#define DUCATI_MEM_CONST_APPM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_SYSM3_ADDR 0x80200000 +#define DUCATI_MEM_HEAP_SYSM3_LEN 0x100000 + +#define DUCATI_MEM_HEAP_APPM3_ADDR 0x80300000 +#define DUCATI_MEM_HEAP_APPM3_LEN 0x1000000 + +#define DUCATI_MEM_MPU_DUCATI_SHMEM_ADDR 0x81300000 +#define DUCATI_MEM_MPU_DUCATI_SHMEM_LEN 0xC00000 + +#define DUCATI_MEM_IPC_SHMEM_ADDR 0x81F00000 +#define DUCATI_MEM_IPC_SHMEM_LEN 0x100000 + +#define DUCATI_MEM_IPC_HEAP0_ADDR 0xA0000000 +#define DUCATI_MEM_IPC_HEAP0_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP1_ADDR 0xA0055000 +#define DUCATI_MEM_IPC_HEAP1_LEN 0x55000 + +#define DUCATI_MEM_IPC_HEAP2_ADDR 0xA00AA000 +#define DUCATI_MEM_IPC_HEAP2_LEN 0x56000 + + +/* Types of mapping attributes */ + +/* MPU address is virtual and needs to be translated to physical addr */ +#define DSP_MAPVIRTUALADDR 0x00000000 +#define DSP_MAPPHYSICALADDR 0x00000001 + +/* Mapped data is big endian */ +#define DSP_MAPBIGENDIAN 0x00000002 +#define DSP_MAPLITTLEENDIAN 0x00000000 + +/* Element size is based on DSP r/w access size */ +#define DSP_MAPMIXEDELEMSIZE 0x00000004 + +/* + * Element size for MMU mapping (8, 16, 32, or 64 bit) + * Ignored if DSP_MAPMIXEDELEMSIZE enabled + */ +#define DSP_MAPELEMSIZE8 0x00000008 +#define DSP_MAPELEMSIZE16 0x00000010 +#define DSP_MAPELEMSIZE32 0x00000020 +#define DSP_MAPELEMSIZE64 0x00000040 + +#define DSP_MAPVMALLOCADDR 0x00000080 +#define DSP_MAPTILERADDR 0x00000100 + + +#define PG_MASK(pg_size) (~((pg_size)-1)) +#define PG_ALIGN_LOW(addr, pg_size) ((addr) & PG_MASK(pg_size)) +#define PG_ALIGN_HIGH(addr, pg_size) (((addr)+(pg_size)-1) & PG_MASK(pg_size)) + + +struct mmu_entry { + u32 ul_phy_addr ; + u32 ul_virt_addr ; + u32 ul_size ; +}; + +struct memory_entry { + u32 ul_virt_addr; + u32 ul_size; +}; + +#if 0 /* Original definitions for OMAP4430. */ +static const struct mmu_entry l4_map[] = { + /* Mailbox 4KB*/ + {L4_PERIPHERAL_MBOX, DUCATI_PERIPHERAL_MBOX, HW_PAGE_SIZE_4KB}, + /* I2C 4KB each */ + {L4_PERIPHERAL_I2C1, DUCATI_PERIPHERAL_I2C1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C2, DUCATI_PERIPHERAL_I2C2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_I2C3, DUCATI_PERIPHERAL_I2C3, HW_PAGE_SIZE_4KB}, + /* DMA 4KB */ + {L4_PERIPHERAL_DMA, DUCATI_PERIPHERAL_DMA, HW_PAGE_SIZE_4KB}, + /* GPIO Banks 4KB each */ + {L4_PERIPHERAL_GPIO1, DUCATI_PERIPHERAL_GPIO1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO2, DUCATI_PERIPHERAL_GPIO2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPIO3, DUCATI_PERIPHERAL_GPIO3, HW_PAGE_SIZE_4KB}, + /* GPTimers 4KB each */ + {L4_PERIPHERAL_GPTIMER3, DUCATI_PERIPHERAL_GPTIMER3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER4, DUCATI_PERIPHERAL_GPTIMER4, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER9, DUCATI_PERIPHERAL_GPTIMER9, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_GPTIMER11, DUCATI_PERIPHERAL_GPTIMER11, + HW_PAGE_SIZE_4KB}, + /* UARTs 4KB each */ + {L4_PERIPHERAL_UART1, DUCATI_PERIPHERAL_UART1, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART2, DUCATI_PERIPHERAL_UART2, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART3, DUCATI_PERIPHERAL_UART3, HW_PAGE_SIZE_4KB}, + {L4_PERIPHERAL_UART4, DUCATI_PERIPHERAL_UART4, + HW_PAGE_SIZE_4KB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* BootVecs regions */ + {0, (PAGE_SIZE_1MB * 2)}, + /* EXTMEM_CORE1: 0x10000000 to 0x100FFFFF */ + {DUCATI_EXTMEM_APPM3_ADDR, DUCATI_EXTMEM_APPM3_LEN}, + /* PRIVATE_SYSM3_DATA*/ + {DUCATI_PRIVATE_SYSM3_DATA_ADDR, DUCATI_PRIVATE_SYSM3_DATA_LEN}, + /* PRIVATE_APPM3_DATA*/ + {DUCATI_PRIVATE_APPM3_DATA_ADDR, DUCATI_PRIVATE_APPM3_DATA_LEN}, + /* SHARED_M3_DATA*/ + {DUCATI_SHARED_M3_DATA_ADDR, DUCATI_SHARED_M3_DATA_LEN}, + /* IPC*/ + {DUCATI_SHARED_IPC_ADDR, DUCATI_SHARED_IPC_LEN}, + /* DMM*/ + {DUCATI_SW_DMM_ADDR, DUCATI_SW_DMM_LEN}, +}; +#endif + +/* OMAP4430 SDC definitions */ +static const struct mmu_entry l4_map[] = { + /* TILER 8-bit and 16-bit modes */ + {L3_TILER_MODE0_1_ADDR, DUCATI_TILER_MODE0_1_ADDR, + (HW_PAGE_SIZE_16MB * 16)}, + /* TILER: Pages-mode */ + {L3_TILER_MODE3_ADDR, DUCATI_TILER_MODE3_ADDR, + (HW_PAGE_SIZE_16MB * 8)}, + /* L4_CFG: Covers all modules in L4_CFG 16MB*/ + {L4_PERIPHERAL_L4CFG, DUCATI_PERIPHERAL_L4CFG, HW_PAGE_SIZE_16MB}, + /* L4_PER: Covers all modules in L4_PER 16MB*/ + {L4_PERIPHERAL_L4PER, DUCATI_PERIPHERAL_L4PER, HW_PAGE_SIZE_16MB}, + /* IVA_HD Config: Covers all modules in IVA_HD Config space 16MB */ + {L3_IVAHD_CONFIG, DUCATI_IVAHD_CONFIG, HW_PAGE_SIZE_16MB}, + /* IVA_HD SL2: Covers all memory in IVA_HD SL2 space 16MB */ + {L3_IVAHD_SL2, DUCATI_IVAHD_SL2, HW_PAGE_SIZE_16MB}, +}; + +static const struct memory_entry l3_memory_regions[] = { + /* MEM_IPC_HEAP0, MEM_IPC_HEAP1, MEM_IPC_HEAP2 */ + {DUCATI_MEM_IPC_HEAP0_ADDR, PAGE_SIZE_1MB}, + /* MEM_INTVECS_SYSM3, MEM_INTVECS_APPM3, MEM_CODE_SYSM3, + MEM_CODE_APPM3 */ + {0, PAGE_SIZE_16MB}, + /* MEM_CONST_SYSM3, MEM_CONST_APPM3, MEM_HEAP_SYSM3, MEM_HEAP_APPM3, + MEM_MPU_DUCATI_SHMEM, MEM_IPC_SHMEM */ + {DUCATI_MEM_CONST_SYSM3_ADDR, (PAGE_SIZE_16MB * 2)}, +}; + + +void dbg_print_ptes(bool ashow_inv_entries, bool ashow_repeat_entries); +int ducati_setup(void); +void ducati_destroy(void); +u32 get_ducati_virt_mem(); +void unmap_ducati_virt_mem(u32 shm_virt_addr); +int ducati_mem_map(u32 va, u32 da, u32 num_bytes, u32 map_attr); +int ducati_mem_unmap(u32 da, u32 num_bytes); +u32 user_va2pa(struct mm_struct *mm, u32 address); +inline u32 ducati_mem_virtToPhys(u32 da); +#endif /* _DDUCATIMMU_ENABLER_H_*/ diff --git a/arch/arm/plat-omap/include/syslink/gate_remote.h b/arch/arm/plat-omap/include/syslink/gate_remote.h new file mode 100644 index 000000000000..e8115d59535a --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gate_remote.h @@ -0,0 +1,34 @@ +/* + * gate_remote.h + * + * This includes the functions to handle remote gates + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTE_H_ +#define _GATE_REMOTE_H_ + +#include <linux/types.h> + +/* + * This function is used to enter in to a remote gate + */ +int gate_remote_enter(void *ghandle, u32 key); + +/* + * This function is used to leave from a remote gate + */ +int gate_remote_leave(void *ghandle, u32 key); + +#endif /* _GATE_REMOTE_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/gatepeterson.h b/arch/arm/plat-omap/include/syslink/gatepeterson.h new file mode 100755 index 000000000000..f2e3f78bf146 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatepeterson.h @@ -0,0 +1,167 @@ +/* + * gatepeterson.h + * + * The Gate Peterson Algorithm for mutual exclusion of shared memory. + * Current implementation works for 2 processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEPETERSON_H_ +#define _GATEPETERSON_H_ + +#include <linux/types.h> + +/* + * GATEPETERSON_MODULEID + * Unique module ID + */ +#define GATEPETERSON_MODULEID (0xF415) + +/* + * A set of context protection levels that each correspond to + * single processor gates used for local protection + */ +enum gatepeterson_protect { + GATEPETERSON_PROTECT_DEFAULT = 0, + GATEPETERSON_PROTECT_NONE = 1, + GATEPETERSON_PROTECT_INTERRUPT = 2, + GATEPETERSON_PROTECT_TASKLET = 3, + GATEPETERSON_PROTECT_THREAD = 4, + GATEPETERSON_PROTECT_PROCESS = 5, + GATEPETERSON_PROTECT_END_VALUE = 6 +}; + +/* + * Structure defining config parameters for the Gate Peterson + * module + */ +struct gatepeterson_config { + enum gatepeterson_protect default_protection; + /*!< Default module-wide local context protection level. The level of + * protection specified here determines which local gate is created per + * GatePeterson instance for local protection during create. The instance + * configuration parameter may be usedto override this module setting per + * instance. The configuration used here should reflect both the context + * in which enter and leave are to be called,as well as the maximum level + * of protection needed locally. + */ + u32 max_name_len; /* GP name len */ + bool use_nameserver; + /*!< Whether to have this module use the NameServer or not. If the + * NameServer is not needed, set this configuration parameter to false. + * This informs GatePeterson not to pull in the NameServer module. + * In this case, all names passed into create and open are ignored. + */ +}; + +/* + * Structure defining config parameters for the Gate Peterson + * instances + */ +struct gatepeterson_params { + void *shared_addr; + /* Address of the shared memory. The creator must supply a cache-aligned + * address in shared memory that will be used to store shared state + * information. + */ + + u32 shared_addr_size; + /* Size of the shared memory region. Can use gatepeterson_shared_memreq + * call to determine the required size. + */ + + char *name; + /* If using nameserver, name of this instance. The name (if not NULL) must + * be unique among all gatepeterson instances in the entire system. + */ + + enum gatepeterson_protect local_protection; + /* Local gate protection level. The default value, (Protect_DEFAULT) + * results in inheritance from module-level defaultProtection. This + * instance setting should be set to an alternative only if a different + * local protection level is needed for the instance. + */ + bool use_nameserver; + /* Whether to have this module use the nameserver or not. If the + * nameserver is not needed, set this configuration parameter to + * false.This informs gatepeterson not to pull in the nameaerver + * module. In this case, all names passed into create and open are + * ignored. + */ +}; + +/* + * Function to initialize the parameter structure + */ +void gatepeterson_get_config(struct gatepeterson_config *config); + +/* + * Function to initialize GP module + */ +int gatepeterson_setup(const struct gatepeterson_config *config); + +/* + * Function to destroy the GP module + */ +int gatepeterson_destroy(void); + +/* + * Function to initialize the parameter structure + */ +void gatepeterson_params_init(void *handle, + struct gatepeterson_params *params); + +/* + * Function to create an instance of GatePeterson + */ +void *gatepeterson_create(const struct gatepeterson_params *params); + +/* + * Function to delete an instance of GatePeterson + */ +int gatepeterson_delete(void **gphandle); + +/* + * Function to open a previously created instance + */ +int gatepeterson_open(void **gphandle, + struct gatepeterson_params *params); + +/* + * Function to close a previously opened instance + */ +int gatepeterson_close(void **gphandle); + +/* + * Function to enter the gate peterson + */ +u32 gatepeterson_enter(void *gphandle); + +/* + *Function to leave the gate peterson + */ +void gatepeterson_leave(void *gphandle, u32 flag); + + +/* + * Returns the gatepeterson kernel object pointer + */ +void *gatepeterson_get_knl_handle(void **gpHandle); + +/* + * Function to return the shared memory requirement + */ +u32 gatepeterson_shared_memreq(const struct gatepeterson_params *params); + +#endif /* _GATEPETERSON_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/gatepeterson_ioctl.h b/arch/arm/plat-omap/include/syslink/gatepeterson_ioctl.h new file mode 100755 index 000000000000..ed7ab86b75bc --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gatepeterson_ioctl.h @@ -0,0 +1,193 @@ +/* + * gatepeterson_ioctl.h + * + * The Gate Peterson Algorithm for mutual exclusion of shared memory. + * Current implementation works for 2 processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _GATEPETERSON_IOCTL_ +#define _GATEPETERSON_IOCTL_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <gatepeterson.h> + +enum CMD_GATEPETERSON { + GATEPETERSON_GETCONFIG = GATEPETERSON_BASE_CMD, + GATEPETERSON_SETUP, + GATEPETERSON_DESTROY, + GATEPETERSON_PARAMS_INIT, + GATEPETERSON_CREATE, + GATEPETERSON_DELETE, + GATEPETERSON_OPEN, + GATEPETERSON_CLOSE, + GATEPETERSON_ENTER, + GATEPETERSON_LEAVE, + GATEPETERSON_SHAREDMEMREQ +}; + +/* + * IOCTL command IDs for gatepeterson + */ + +/* + * Command for gatepeterson_get_config + */ +#define CMD_GATEPETERSON_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_GETCONFIG, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_setup + */ +#define CMD_GATEPETERSON_SETUP _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_SETUP, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_setup + */ +#define CMD_GATEPETERSON_DESTROY _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_DESTROY, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_destroy + */ +#define CMD_GATEPETERSON_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_PARAMS_INIT, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_create + */ +#define CMD_GATEPETERSON_CREATE _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_CREATE, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_delete + */ +#define CMD_GATEPETERSON_DELETE _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_DELETE, \ + struct gatepeterson_cmd_args) +/* + * Command for gatepeterson_open + */ +#define CMD_GATEPETERSON_OPEN _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_OPEN, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_close + */ +#define CMD_GATEPETERSON_CLOSE _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_CLOSE, \ + struct gatepeterson_cmd_args) +/* + * Command for gatepeterson_enter + */ +#define CMD_GATEPETERSON_ENTER _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_ENTER, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_leave + */ +#define CMD_GATEPETERSON_LEAVE _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_LEAVE, \ + struct gatepeterson_cmd_args) + +/* + * Command for gatepeterson_shared_memreq + */ +#define CMD_GATEPETERSON_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + GATEPETERSON_SHAREDMEMREQ, \ + struct gatepeterson_cmd_args) + +/* + * Command arguments for gatepeterson + */ +union gatepeterson_arg { + struct { + void *handle; + struct gatepeterson_params *params; + } params_init; + + struct { + struct gatepeterson_config *config; + } get_config; + + struct { + struct gatepeterson_config *config; + } setup; + + struct { + void *handle; + struct gatepeterson_params *params; + u32 name_len; + u32 shared_addr_srptr; + } create; + + struct { + void *handle; + } delete; + + struct { + void *handle; + struct gatepeterson_params *params; + u32 name_len; + u32 shared_addr_srptr; + } open; + + struct { + void *handle; + } close; + + struct { + void *handle; + u32 flags; + } enter; + + struct { + void *handle; + u32 flags; + } leave; + + struct { + void *handle; + struct gatepeterson_params *params; + u32 bytes; + } shared_memreq; + +}; + +/* + * Command arguments for gatepeterson + */ +struct gatepeterson_cmd_args { + union gatepeterson_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for gatepeterson module + */ +int gatepeterson_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _GATEPETERSON_IOCTL_ */ + diff --git a/arch/arm/plat-omap/include/syslink/gt.h b/arch/arm/plat-omap/include/syslink/gt.h new file mode 100644 index 000000000000..95e3feb18e7b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/gt.h @@ -0,0 +1,320 @@ + +/* + * gt.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * ======== gt.h ======== + * Purpose: + * There are two definitions that affect which portions of trace + * are acutally compiled into the client: GT_TRACE and GT_ASSERT. If + * GT_TRACE is set to 0 then all trace statements (except for assertions) + * will be compiled out of the client. If GT_ASSERT is set to 0 then + * assertions will be compiled out of the client. GT_ASSERT can not be + * set to 0 unless GT_TRACE is also set to 0 (i.e. GT_TRACE == 1 implies + * GT_ASSERT == 1). + * + *! Revision History + *! ================ + *! 02-Feb-2000 rr: Renamed this file to gtce.h. GT CLASS and trace + *! definitions are WinCE Specific. + *! 03-Jan-1997 ge Replaced "GT_" prefix to GT_Config structure members + *! to eliminate preprocessor confusion with other macros. + */ +#include <linux/types.h> +#ifndef GT_ +#define GT_ + +#ifndef GT_TRACE +#define GT_TRACE 0 /* 0 = "trace compiled out"; 1 = "trace active" */ +#endif + +/* #include <syslink/host_os.h> */ + +typedef s32(*Fxn)(); /* generic function type */ + + +#if !defined(GT_ASSERT) || GT_TRACE +#define GT_ASSERT 1 +#endif + +struct GT_Config { + Fxn PRINTFXN; + Fxn PIDFXN; + Fxn TIDFXN; + Fxn ERRORFXN; +}; + +extern struct GT_Config *GT; + +struct gt_mask { + char *modName; + u8 *flags; +} ; + +/* + * New GT Class defenitions. + * + * The following are the explanations and how it could be used in the code + * + * - GT_ENTER On Entry to Functions + * + * - GT_1CLASS Display level of debugging status- Object/Automatic + * variables + * - GT_2CLASS ---- do ---- + * + * - GT_3CLASS ---- do ---- + It can be used(recommended) for debug + * status in the ISR, IST + * - GT_4CLASS ---- do ---- + * + * - GT_5CLASS Display entry for module init/exit functions + * + * - GT_6CLASS Warn whenever SERVICES function fails + * + * - GT_7CLASS Warn failure of Critical failures + * + */ + +#define GT_ENTER ((u8)0x01) +#define GT_1CLASS ((u8)0x02) +#define GT_2CLASS ((u8)0x04) +#define GT_3CLASS ((u8)0x08) +#define GT_4CLASS ((u8)0x10) +#define GT_5CLASS ((u8)0x20) +#define GT_6CLASS ((u8)0x40) +#define GT_7CLASS ((u8)0x80) +#define GT_LEAVE ((u8)0x02) + +#ifdef _LINT_ + +/* LINTLIBRARY */ + +/* + * ======== GT_assert ======== + */ +/* ARGSUSED */ +void GT_assert(struct gt_mask mask, s32 expr) +{ +} + +/* + * ======== GT_config ======== + */ +/* ARGSUSED */ +void GT_config(struct GT_Config config) +{ +} + +/* + * ======== GT_create ======== + */ +/* ARGSUSED */ +void GT_create(struct gt_mask *mask, char *modName) +{ +} + +/* + * ======== GT_curline ======== + * Purpose: + * Returns the current source code line number. Is useful for performing + * branch testing using trace. For example, + * + * gt_1trace(curTrace, GT_1CLASS, + * "in module XX_mod, executing line %u\n", GT_curline()); + */ +/* ARGSUSED */ +u16 GT_curline(void) +{ + return (u16)NULL; +} + +/* + * ======== GT_exit ======== + */ +/* ARGSUSED */ +void GT_exit(void) +{ +} + +/* + * ======== GT_init ======== + */ +/* ARGSUSED */ +void GT_init(void) +{ +} + +/* + * ======== GT_query ======== + */ +/* ARGSUSED */ +bool GT_query(struct gt_mask mask, u8 class) +{ + return false; +} + +/* + * ======== GT_set ======== + * sets trace mask according to settings + */ + +/* ARGSUSED */ +void GT_set(char *settings) +{ +} + +/* + * ======== GT_setprintf ======== + * sets printf function + */ + +/* ARGSUSED */ +void GT_setprintf(Fxn fxn) +{ +} + +/* ARGSUSED */ +void gt_0trace(struct gt_mask mask, u8 class, char *format) +{ +} + +/* ARGSUSED */ +void gt_1trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_2trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_3trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_4trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void gt_5trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +/* ARGSUSED */ +void GT_6trace(struct gt_mask mask, u8 class, char *format, ...) +{ +} + +#else + +#define GT_BOUND 26 /* 26 letters in alphabet */ + +extern void _GT_create(struct gt_mask *mask, char *modName); + +#define GT_exit() + +extern void GT_init(void); +extern void _GT_set(char *str); +extern s32 _GT_trace(struct gt_mask *mask, char *format, ...); + +#if GT_ASSERT == 0 + +#define GT_assert(mask, expr) +#define GT_config(config) +#define GT_configInit(config) +#define GT_seterror(fxn) + +#else + +extern struct GT_Config _GT_params; + +#define GT_assert(mask, expr) \ + (!(expr) ? \ + printk(KERN_ALERT "assertion violation: %s, line %d\n", \ + __FILE__, __LINE__), NULL : NULL) + +#define GT_config(config) (_GT_params = *(config)) +#define GT_configInit(config) (*(config) = _GT_params) +#define GT_seterror(fxn) (_GT_params.ERRORFXN = (Fxn)(fxn)) + +#endif + +#if GT_TRACE == 0 + +#define GT_curline() ((u16)__LINE__) +#define GT_create(mask, modName) +#define GT_exit() +#define GT_init() +#define GT_set(settings) +#define GT_setprintf(fxn) + +#define GT_query(mask, class) false + +#define gt_0trace(mask, class, format) +#define gt_1trace(mask, class, format, arg1) +#define gt_2trace(mask, class, format, arg1, arg2) +#define gt_3trace(mask, class, format, arg1, arg2, arg3) +#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) +#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) +#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) + +#else /* GT_TRACE == 1 */ + +#define GT_create(mask, modName) _GT_create((mask), (modName)) +#define GT_curline() ((u16)__LINE__) +#define GT_set(settings) _GT_set(settings) +#define GT_setprintf(fxn) (_GT_params.PRINTFXN = (Fxn)(fxn)) + +#define GT_query(mask, class) ((*(mask).flags & (class))) + +#define gt_0trace(mask, class, format) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format)) : 0) + +#define gt_1trace(mask, class, format, arg1) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1)) : 0) + +#define gt_2trace(mask, class, format, arg1, arg2) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2)) : 0) + +#define gt_3trace(mask, class, format, arg1, arg2, arg3) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3)) : 0) + +#define gt_4trace(mask, class, format, arg1, arg2, arg3, arg4) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4)) : 0) + +#define gt_5trace(mask, class, format, arg1, arg2, arg3, arg4, arg5) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5)) \ + : 0) + +#define GT_6trace(mask, class, format, arg1, arg2, arg3, arg4, arg5, arg6) \ + ((*(mask).flags & (class)) ? \ + _GT_trace(&(mask), (format), (arg1), (arg2), (arg3), (arg4), (arg5), \ + (arg6)) : 0) + +#endif /* GT_TRACE */ + +#endif /* _LINT_ */ + +#endif /* GTCE_ */ diff --git a/arch/arm/plat-omap/include/syslink/heap.h b/arch/arm/plat-omap/include/syslink/heap.h new file mode 100755 index 000000000000..f03a692a71ab --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heap.h @@ -0,0 +1,91 @@ +/* + * heap.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAP_H_ +#define _HEAP_H_ + +#include <linux/types.h> + +/* + * Structure defining memory related statistics + */ +struct memory_stats{ + u32 *total_size; /* Total memory size */ + u32 *total_free_size; /* Total free memory size */ + u32 *largest_free_size; /* Largest free memory size */ +}; + +/*! + * ======== extendedstats ======== + * Stats structure for the get_extended_stats API. + * + * max_allocated_blocks: The maximum number of blocks allocated + * from this heap at any single point in time during the lifetime of this + * heap instance. + * + * num_allocated_blocks: The total number of blocks currently + * allocated in this Heap instance. + */ +struct heap_extended_stats { + u32 max_allocated_blocks; + u32 num_allocated_blocks; +}; + +/* + * Structure defining config parameters for the heapbuf module + */ +struct heap_config { + u32 max_name_len; /* Maximum length of name */ + bool track_max_allocs; /* Track the max number of allocated blocks */ +}; + +/* + * Structure for the handle for the heap + */ +struct heap_object { + void* (*alloc) (void *handle, u32 size, u32 align); + int (*free) (void *handle, void *block, u32 size); + int (*get_stats) (void *handle, struct memory_stats *stats); + int (*get_extended_stats) (void *handle, + struct heap_extended_stats *stats); + void *obj; +}; + +/* + * Allocate a block + */ +void *heap_alloc(void *handle, u32 size, u32 align); + +/* + * Frees the block to this Heap + */ +int heap_free(void *handle, void *block, u32 size); + +/* + * Get heap statistics + */ +int heap_get_stats(void *handle, struct memory_stats *stats); + +/* + * Get heap extended statistics + */ +int heap_get_extended_stats(void *hphandle, + struct heap_extended_stats *stats); + +#endif /* _HEAP_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/heapbuf.h b/arch/arm/plat-omap/include/syslink/heapbuf.h new file mode 100755 index 000000000000..3667c4675d49 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapbuf.h @@ -0,0 +1,152 @@ +/* + * heapbuf.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPBUF_H_ +#define _HEAPBUF_H_ + +#include <linux/types.h> +#include <heap.h> +#include <listmp.h> + +/*! + * @def LISTMP_MODULEID + * @brief Unique module ID. + */ +#define HEAPBUF_MODULEID (0x4cd5) + +/* + * Creation of Heap Buf succesful. +*/ +#define HEAPBUF_CREATED (0x05251995) + +/* + * Version. + */ +#define HEAPBUF_VERSION (1) + +/* + * Structure defining config parameters for the HeapBuf module. + */ +struct heapbuf_config { + u32 max_name_len; /* Maximum length of name */ + bool use_nameserver; /* To have this module use the NameServer or not */ + bool track_max_allocs; /* Track the maximum number of allocated blocks */ +}; + +/* + * Structure defining parameters for the HeapBuf module + */ +struct heapbuf_params { + void *gate; + bool exact; /* Only allocate on exact match of rquested size */ + char *name; /* Name when using nameserver */ + int resource_id; /* Resource id of the hardware linked list */ + bool cache_flag; /* Whether to perform cache coherency calls */ + u32 align; /* Alignment (in MAUs, power of 2) of each block */ + u32 num_blocks; /* Number of fixed-size blocks */ + u32 block_size; /* Size (in MAUs) of each block*/ + void *shared_addr; /* Physical address of the shared memory */ + u32 shared_addr_size; /* Size of shareAddr */ + void *shared_buf; /* Physical address of the shared buffers */ + u32 shared_buf_size; /* Size of sharedBuf */ +}; + +/* + * Stats structure for the getExtendedStats API. + */ +struct heapbuf_extended_stats { + u32 max_allocated_blocks; + /* maximum number of blocks allocated from this heap instance */ + u32 num_allocated_blocks; + /* total number of blocks currently allocated from this heap instance*/ +}; + + +/* + * Function to get default configuration for the heapbuf module + */ +int heapbuf_get_config(struct heapbuf_config *cfgparams); + +/* + * Function to setup the heapbuf module + */ +int heapbuf_setup(const struct heapbuf_config *cfg); + +/* + * Function to destroy the heapbuf module + */ +int heapbuf_destroy(void); + +/* Initialize this config-params structure with supplier-specified + * defaults before instance creation + */ +void heapbuf_params_init(void *handle, struct heapbuf_params *params); + +/* + * Creates a new instance of heapbuf module + */ +void *heapbuf_create(const struct heapbuf_params *params); + +/* + * Deletes a instance of heapbuf module + */ +int heapbuf_delete(void **handle_ptr); + +/* + * Opens a created instance of heapbuf module + */ +int heapbuf_open(void **handle_ptr, struct heapbuf_params *params); + +/* + * Closes previously opened/created instance of heapbuf module + */ +int heapbuf_close(void *handle_ptr); + +/* + * Returns the amount of shared memory required for creation + * of each instance + */ +int heapbuf_shared_memreq(const struct heapbuf_params *params, u32 *buf_size); + +/* + * Allocate a block + */ +void *heapbuf_alloc(void *hphandle, u32 size, u32 align); + +/* + * Frees the block to this heapbuf + */ +int heapbuf_free(void *hphandle, void *block, u32 size); + +/* + * Get memory statistics + */ +int heapbuf_get_stats(void *hphandle, struct memory_stats *stats); + +/* + * Indicate whether the heap may block during an alloc or free call + */ +bool heapbuf_isblocking(void *handle); + +/* + * Get extended statistics + */ +int heapbuf_get_extended_stats(void *hphandle, + struct heapbuf_extended_stats *stats); + +#endif /* _HEAPBUF_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/heapbuf_ioctl.h b/arch/arm/plat-omap/include/syslink/heapbuf_ioctl.h new file mode 100755 index 000000000000..80165dcfc436 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/heapbuf_ioctl.h @@ -0,0 +1,215 @@ +/* + * heapbuf_ioctl.h + * + * Heap module manages fixed size buffers that can be used + * in a multiprocessor system with shared memory. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _HEAPBUF_IOCTL_ +#define _HEAPBUF_IOCTL_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <heap.h> +#include <heapbuf.h> + + +enum CMD_HEAPBUF { + HEAPBUF_GETCONFIG = HEAPBUF_BASE_CMD, + HEAPBUF_SETUP, + HEAPBUF_DESTROY, + HEAPBUF_PARAMS_INIT, + HEAPBUF_CREATE, + HEAPBUF_DELETE, + HEAPBUF_OPEN, + HEAPBUF_CLOSE, + HEAPBUF_ALLOC, + HEAPBUF_FREE, + HEAPBUF_SHAREDMEMREQ, + HEAPBUF_GETSTATS, + HEAPBUF_GETEXTENDEDSTATS +}; + +/* + * Command for heapbuf_get_config + */ +#define CMD_HEAPBUF_GETCONFIG _IOWR(IPC_IOC_MAGIC, HEAPBUF_GETCONFIG,\ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_setup + */ +#define CMD_HEAPBUF_SETUP _IOWR(IPC_IOC_MAGIC, HEAPBUF_SETUP, \ + struct heapbuf_cmd_args) +/* + * Command for heapbuf_destroy + */ +#define CMD_HEAPBUF_DESTROY _IOWR(IPC_IOC_MAGIC, HEAPBUF_DESTROY, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_prams_init + */ +#define CMD_HEAPBUF_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + HEAPBUF_PARAMS_INIT, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_create + */ +#define CMD_HEAPBUF_CREATE _IOWR(IPC_IOC_MAGIC, HEAPBUF_CREATE, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_delete + */ +#define CMD_HEAPBUF_DELETE _IOWR(IPC_IOC_MAGIC, HEAPBUF_DELETE, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_open + */ +#define CMD_HEAPBUF_OPEN _IOWR(IPC_IOC_MAGIC, HEAPBUF_OPEN, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_close + */ +#define CMD_HEAPBUF_CLOSE _IOWR(IPC_IOC_MAGIC, HEAPBUF_CLOSE, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_alloc + */ +#define CMD_HEAPBUF_ALLOC _IOWR(IPC_IOC_MAGIC, HEAPBUF_ALLOC, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_free + */ +#define CMD_HEAPBUF_FREE _IOWR(IPC_IOC_MAGIC, HEAPBUF_FREE, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_shared_memreq + */ +#define CMD_HEAPBUF_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + HEAPBUF_SHAREDMEMREQ, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_get_stats + */ +#define CMD_HEAPBUF_GETSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPBUF_GETSTATS, \ + struct heapbuf_cmd_args) + +/* + * Command for heapbuf_get_extended_stats + */ +#define CMD_HEAPBUF_GETEXTENDEDSTATS _IOWR(IPC_IOC_MAGIC, \ + HEAPBUF_GETEXTENDEDSTATS, \ + struct heapbuf_cmd_args) + + +/* + * Command arguments for heapbuf + */ +union heapbuf_arg { + struct { + void *handle; + struct heapbuf_params *params; + } params_init; + + struct { + struct heapbuf_config *config; + } get_config; + + struct { + struct heapbuf_config *config; + } setup; + + struct { + void *handle; + struct heapbuf_params *params; + u32 name_len; + u32 *shared_addr_srptr; + u32 *shared_buf_srptr; + void *knl_gate; + } create; + + struct { + void *handle; + } delete; + + struct { + void *handle; + struct heapbuf_params *params; + u32 name_len; + u32 *shared_addr_srptr; + void *knl_gate; + } open; + + struct { + void *handle; + } close; + + struct { + void *handle; + u32 size; + u32 align; + u32 *block_srptr; + } alloc; + + struct { + void *handle; + u32 *block_srptr; + u32 size; + } free; + + struct { + void *handle; + struct memory_stats *stats; + } get_stats; + + struct { + void *handle; + struct heapbuf_extended_stats *stats; + } get_extended_stats; + + struct { + void *handle; + struct heapbuf_params *params; + u32 buf_size; + u32 bytes; + } shared_memreq; +}; + +/* + * Command arguments for heapbuf + */ +struct heapbuf_cmd_args{ + union heapbuf_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for heapbuf module + */ +int heapbuf_ioctl(struct inode *pinode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _HEAPBUF_IOCTL_ */ diff --git a/arch/arm/plat-omap/include/syslink/host_os.h b/arch/arm/plat-omap/include/syslink/host_os.h new file mode 100755 index 000000000000..e0f02c3cfe88 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/host_os.h @@ -0,0 +1,72 @@ + +/* + * host_os.h + * + * DSP-BIOS Bridge driver support functions for TI OMAP processors. + * + * Copyright (C) 2008 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * ======== windows.h ======== + * + *! Revision History + *! ================ + *! 08-Mar-2004 sb Added cacheflush.h to support Dynamic Memory Mapping feature + *! 16-Feb-2004 sb Added headers required for consistent_alloc + */ + +#ifndef _HOST_OS_H_ +#define _HOST_OS_H_ + +#include <linux/autoconf.h> +#include <asm/system.h> +#include <asm/atomic.h> +#include <linux/semaphore.h> +#include <linux/uaccess.h> +#include <asm/irq.h> +#include <linux/io.h> +#include <linux/syscalls.h> +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/stddef.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/sched.h> +#include <linux/fs.h> +#include <linux/file.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/ctype.h> +#include <linux/mm.h> +#include <linux/device.h> +#include <linux/vmalloc.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/pagemap.h> +#include <asm/cacheflush.h> +#include <linux/dma-mapping.h> + +/* ----------------------------------- Macros */ + +#define SEEK_SET 0 /* Seek from beginning of file. */ +#define SEEK_CUR 1 /* Seek from current position. */ +#define SEEK_END 2 /* Seek from end of file. */ + +/* TODO -- Remove, once BP defines them */ +#define INT_MAIL_MPU_IRQ 26 +#define INT_DSP_MMU_IRQ 28 + +#endif diff --git a/arch/arm/plat-omap/include/syslink/hw_defs.h b/arch/arm/plat-omap/include/syslink/hw_defs.h new file mode 100755 index 000000000000..440dbb14445e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_defs.h @@ -0,0 +1,63 @@ +/* + * hw_defs.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __HW_DEFS_H +#define __HW_DEFS_H + +#include <syslink/GlobalTypes.h> + +/* Page size */ +#define HW_PAGE_SIZE_4KB 0x1000 +#define HW_PAGE_SIZE_64KB 0x10000 +#define HW_PAGE_SIZE_1MB 0x100000 +#define HW_PAGE_SIZE_16MB 0x1000000 + +/* hw_status: return type for HW API */ +typedef long hw_status; + +/* hw_set_clear_t: Enumerated Type used to set and clear any bit */ +enum hw_set_clear_t { + HW_CLEAR, + HW_SET +} ; + +/* hw_endianism_t: Enumerated Type used to specify the endianism + * Do NOT change these values. They are used as bit fields. */ +enum hw_endianism_t { + HW_LITTLE_ENDIAN, + HW_BIG_ENDIAN + +} ; + +/* hw_elemnt_siz_t: Enumerated Type used to specify the element size + * Do NOT change these values. They are used as bit fields. */ +enum hw_elemnt_siz_t { + HW_ELEM_SIZE_8BIT, + HW_ELEM_SIZE_16BIT, + HW_ELEM_SIZE_32BIT, + HW_ELEM_SIZE_64BIT + +} ; + +/* HW_IdleMode_t: Enumerated Type used to specify Idle modes */ +enum HW_IdleMode_t { + HW_FORCE_IDLE, + HW_NO_IDLE, + HW_SMART_IDLE +} ; + +#endif /* __HW_DEFS_H */ diff --git a/arch/arm/plat-omap/include/syslink/hw_mbox.h b/arch/arm/plat-omap/include/syslink/hw_mbox.h new file mode 100755 index 000000000000..f50ef782e66f --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_mbox.h @@ -0,0 +1,447 @@ +/* + * hw_mbox.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __MBOX_H +#define __MBOX_H + +#include <syslink/hw_defs.h> + + +#define HW_MBOX_INT_NEW_MSG 0x1 +#define HW_MBOX_INT_NOT_FULL 0x2 +#define HW_MBOX_INT_ALL 0x3 + +/* + * DEFINITION: HW_MBOX_MAX_NUM_MESSAGES + * + * DESCRIPTION: Maximum number of messages that mailbox can hald at a time. + * + * + */ + +#define HW_MBOX_MAX_NUM_MESSAGES 4 + + + /* width in bits of MBOX Id */ +#define HW_MBOX_ID_WIDTH 2 + + +/* + * TYPE: enum hw_mbox_id_t + * + * DESCRIPTION: Enumerated Type used to specify Mail Box Sub Module Id Number + * + * + */ + enum hw_mbox_id_t { + HW_MBOX_ID_0, + HW_MBOX_ID_1, + HW_MBOX_ID_2, + HW_MBOX_ID_3, + HW_MBOX_ID_4, + HW_MBOX_ID_5 + }; + +/* + * TYPE: enum hw_mbox_userid_t + * + * DESCRIPTION: Enumerated Type used to specify Mail box User Id + * + * + */ + enum hw_mbox_userid_t { + HW_MBOX_U0_ARM11, + HW_MBOX_U1_UMA, + HW_MBOX_U2_IVA, + HW_MBOX_U3_ARM11 + }; + +#if defined(OMAP3430) +/* +* TYPE: mailbox_context +* +* DESCRIPTION: Mailbox context settings +* +* +*/ +struct mailbox_context { + unsigned long sysconfig; + unsigned long irqEnable0; + unsigned long irqEnable1; +}; +#endif/* defined(OMAP3430)*/ + +/* +* FUNCTION : hw_mbox_msg_read +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to read +* +* OUTPUTS: +* +* Identifier : p_read_value +* Type : unsigned long *const +* Description : Value read from MailBox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: +* : this function reads a unsigned long from the sub module message +* box Specified. if there are no messages in the mailbox +* then and error is returned. +* +*/ +extern long hw_mbox_msg_read( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_read_value + ); + +/* +* FUNCTION : hw_mbox_msg_write +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to write +* +* Identifier : write_value +* Type : const unsigned long +* Description : Value to write to MailBox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE:: this function writes a unsigned long from the sub module message +* box Specified. +* +* +*/ +extern long hw_mbox_msg_write( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const unsigned long write_value + ); + +/* +* FUNCTION : hw_mbox_is_full +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to check +* +* OUTPUTS: +* +* Identifier : p_is_full +* Type : unsigned long *const +* Description : false means mail box not Full +* true means mailbox full. +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function reads the full status register for mailbox. +* +* +*/ +extern long hw_mbox_is_full( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_is_full + ); + +/* ----------------------------------------------------------------- +* FUNCTION : hw_mbox_nomsg_get +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to get num messages +* +* OUTPUTS: +* +* Identifier : p_num_msg +* Type : unsigned long *const +* Description : Number of messages in mailbox +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Inavlid ID input at parameter +* +* PURPOSE: +* : this function gets number of messages in a specified mailbox. +* +* +*/ +extern long hw_mbox_nomsg_get( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + unsigned long *const p_num_msg + ); + +/* +* FUNCTION : hw_mbox_event_enable +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to enable +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to enable +* +* Identifier : enableIrq +* Type : const unsigned long +* Description : Irq value to enable +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function enables the specified IRQ. +* +* +*/ +extern long hw_mbox_event_enable( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long events + ); + +/* +* FUNCTION : hw_mbox_event_disable +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to disable +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to disable +* +* Identifier : enableIrq +* Type : const unsigned long +* Description : Irq value to disable +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function disables the specified IRQ. +* +* +*/ +extern long hw_mbox_event_disable( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long events + ); + +/* +* FUNCTION : hw_mbox_event_status +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to clear +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to clear +* +* OUTPUTS: +* +* Identifier : pIrqStatus +* Type : pMBOX_Int_t *const +* Description : The value in IRQ status register +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function gets the status of the specified IRQ. +* +* +*/ +extern long hw_mbox_event_status( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + unsigned long *const p_eventStatus + ); + +/* +* FUNCTION : hw_mbox_event_ack +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* Identifier : mail_box_id +* Type : const enum hw_mbox_id_t +* Description : Mail Box Sub module Id to set +* +* Identifier : user_id +* Type : const enum hw_mbox_userid_t +* Description : Mail box User Id to set +* +* Identifier : irqStatus +* Type : const unsigned long +* Description : The value to write IRQ status +* +* OUTPUTS: +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address Paramater was set to 0 +* RET_INVALID_ID Invalid Id used +* +* PURPOSE: : this function sets the status of the specified IRQ. +* +* +*/ +extern long hw_mbox_event_ack( + const unsigned long base_address, + const enum hw_mbox_id_t mail_box_id, + const enum hw_mbox_userid_t user_id, + const unsigned long event + ); + +#if defined(OMAP3430) +/* --------------------------------------------------------------- +* FUNCTION : hw_mbox_save_settings +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: : this function saves the context of mailbox +* +* ---------------------------------------------------------------- +*/ +extern long hw_mbox_save_settings(unsigned long baseAddres); + +/* +* FUNCTION : hw_mbox_restore_settings +* +* INPUTS: +* +* Identifier : base_address +* Type : const unsigned long +* Description : Base Address of instance of Mailbox module +* +* +* RETURNS: +* +* Type : ReturnCode_t +* Description : RET_OK No errors occured +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL +* RET_INVALID_ID Invalid Id used +* RET_EMPTY Mailbox empty +* +* PURPOSE: : this function restores the context of mailbox +* +* +*/ +extern long hw_mbox_restore_settings(unsigned long baseAddres); +#endif/* defined(OMAP3430)*/ + +#endif /* __MBOX_H */ + diff --git a/arch/arm/plat-omap/include/syslink/hw_mmu.h b/arch/arm/plat-omap/include/syslink/hw_mmu.h new file mode 100755 index 000000000000..a85b2f9ca024 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_mmu.h @@ -0,0 +1,169 @@ +/* + * hw_mbox.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef __HW_MMU_H +#define __HW_MMU_H + +#include <linux/types.h> + +/* Bitmasks for interrupt sources */ +#define HW_MMU_TRANSLATION_FAULT 0x2 +#define HW_MMU_ALL_INTERRUPTS 0x1F + +#define HW_MMU_COARSE_PAGE_SIZE 0x400 + +/* hw_mmu_mixed_size_t: Enumerated Type used to specify whether to follow + CPU/TLB Element size */ +enum hw_mmu_mixed_size_t { + HW_MMU_TLBES, + HW_MMU_CPUES + +} ; + +/* hw_mmu_map_attrs_t: Struct containing MMU mapping attributes */ +struct hw_mmu_map_attrs_t { + enum hw_endianism_t endianism; + enum hw_elemnt_siz_t element_size; + enum hw_mmu_mixed_size_t mixedSize; +} ; + +extern hw_status hw_mmu_enable(const u32 base_address); + +extern hw_status hw_mmu_disable(const u32 base_address); + +extern hw_status hw_mmu_numlocked_set(const u32 base_address, + u32 num_lcked_entries); + +extern hw_status hw_mmu_victim_numset(const u32 base_address, + u32 vctm_entry_num); + +/* For MMU faults */ +extern hw_status hw_mmu_eventack(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_disable(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_enable(const u32 base_address, + u32 irq_mask); + +extern hw_status hw_mmu_event_status(const u32 base_address, + u32 *irq_mask); + +extern hw_status hw_mmu_flt_adr_rd(const u32 base_address, + u32 *addr); + +/* Set the TT base address */ +extern hw_status hw_mmu_ttbset(const u32 base_address, + u32 ttb_phys_addr); + +extern hw_status hw_mmu_twl_enable(const u32 base_address); + +extern hw_status hw_mmu_twl_disable(const u32 base_address); + +extern hw_status hw_mmu_tlb_flush(const u32 base_address, + u32 virtual_addr, + u32 page_size); + +extern hw_status hw_mmu_tlb_flushAll(const u32 base_address); + +extern hw_status hw_mmu_tlb_add(const u32 base_address, + u32 physical_addr, + u32 virtual_addr, + u32 page_size, + u32 entryNum, + struct hw_mmu_map_attrs_t *map_attrs, + enum hw_set_clear_t preserve_bit, + enum hw_set_clear_t valid_bit); + + +/* For PTEs */ +extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va, + u32 physical_addr, + u32 virtual_addr, + u32 page_size, + struct hw_mmu_map_attrs_t *map_attrs); + +extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, + u32 pg_size, + u32 virtual_addr); + +static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va) +{ + u32 pte_addr; + u32 VA_31_to_20; + + VA_31_to_20 = va >> (20 - 2); /* Left-shift by 2 here itself */ + VA_31_to_20 &= 0xFFFFFFFCUL; + pte_addr = l1_base + VA_31_to_20; + + return pte_addr; +} + +static inline u32 hw_mmu_pte_addr_l2(u32 l2_base, u32 va) +{ + u32 pte_addr; + + pte_addr = (l2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC); + + return pte_addr; +} + +static inline u32 hw_mmu_pte_coarsel1(u32 pte_val) +{ + u32 pteCoarse; + + pteCoarse = pte_val & 0xFFFFFC00; + + return pteCoarse; +} + +static inline u32 hw_mmu_pte_sizel1(u32 pte_val) +{ + u32 pte_size = 0; + + if ((pte_val & 0x3) == 0x1) { + /* Points to L2 PT */ + pte_size = HW_MMU_COARSE_PAGE_SIZE; + } + + if ((pte_val & 0x3) == 0x2) { + if (pte_val & (1 << 18)) + pte_size = HW_PAGE_SIZE_16MB; + else + pte_size = HW_PAGE_SIZE_1MB; + } + + return pte_size; +} + +static inline u32 hw_mmu_pte_sizel2(u32 pte_val) +{ + u32 pte_size = 0; + + if (pte_val & 0x2) + pte_size = HW_PAGE_SIZE_4KB; + else if (pte_val & 0x1) + pte_size = HW_PAGE_SIZE_64KB; + + return pte_size; +} +extern hw_status hw_mmu_tlb_dump(u32 base_address, bool shw_inv_entries); + +extern u32 hw_mmu_pte_phyaddr(u32 pte_val, u32 pte_size); + +#endif /* __HW_MMU_H */ diff --git a/arch/arm/plat-omap/include/syslink/hw_ocp.h b/arch/arm/plat-omap/include/syslink/hw_ocp.h new file mode 100755 index 000000000000..7277bbfcde33 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/hw_ocp.h @@ -0,0 +1,60 @@ +/* + * hw_ocp.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef __HW_OCP_H +#define __HW_OCP_H + +#include <syslink/GlobalTypes.h> +#include <syslink/hw_ocp.h> +#include <syslink/hw_defs.h> +#include <syslink/MBXRegAcM.h> +#include <syslink/MBXAccInt.h> + + +/* +* TYPE: HW_IdleMode_t +* +* DESCRIPTION: Enumerated Type for idle modes in OCP SYSCONFIG register +* +* +*/ +enum hal_ocp_idlemode_t { + HW_OCP_FORCE_IDLE, + HW_OCP_NO_IDLE, + HW_OCP_SMART_IDLE +}; + +extern long hw_ocp_soft_reset(const unsigned long base_address); + +extern long hw_ocp_soft_reset_isdone(const unsigned long base_address, + unsigned long *reset_is_done); + +extern long hw_ocp_idle_modeset(const unsigned long base_address, + enum hal_ocp_idlemode_t idle_mode); + +extern long hw_ocp_idlemode_get(const unsigned long base_address, + enum hal_ocp_idlemode_t *idle_mode); + +extern long hw_ocp_autoidle_set(const unsigned long base_address, + enum hw_set_clear_t auto_idle); + +extern long hw_ocp_autoidle_get(const unsigned long base_address, + enum hw_set_clear_t *auto_idle); + +#endif /* __HW_OCP_H */ + diff --git a/arch/arm/plat-omap/include/syslink/ipc_ioctl.h b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h new file mode 100755 index 000000000000..5a5078fcf3bd --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/ipc_ioctl.h @@ -0,0 +1,92 @@ +/* + * ipc_ioctl.h + * + * Base file for all TI OMAP IPC ioctl's. + * Linux-OMAP IPC has allocated base 0xEE with a range of 0x00-0xFF. + * (need to get the real one from open source maintainers) + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _IPC_IOCTL_H +#define _IPC_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/fs.h> + +#define IPC_IOC_MAGIC 0xE0 +#define IPC_IOC_BASE 2 + +enum ipc_command_count { + MULTIPROC_CMD_NOS = 4, + NAMESERVER_CMD_NOS = 13, + HEAPBUF_CMD_NOS = 13, + SHAREDREGION_CMD_NOS = 10, + GATEPETERSON_CMD_NOS = 11, + LISTMP_SHAREDMEMORY_CMD_NOS = 18, + MESSAGEQ_CMD_NOS = 17, + MESSAGEQ_TRANSPORTSHM_CMD_NOS = 9, + NAMESERVERREMOTENOTIFY_CMD_NOS = 8, + SYSMGR_CMD_NOS = 5, + SYSMEMMGR_CMD_NOS = 6 +}; + +enum ipc_command_ranges { + MULTIPROC_BASE_CMD = IPC_IOC_BASE, + MULTIPROC_END_CMD = (MULTIPROC_BASE_CMD + \ + MULTIPROC_CMD_NOS - 1), + + NAMESERVER_BASE_CMD = 10, + NAMESERVER_END_CMD = (NAMESERVER_BASE_CMD + \ + NAMESERVER_CMD_NOS - 1), + + HEAPBUF_BASE_CMD = 30, + HEAPBUF_END_CMD = (HEAPBUF_BASE_CMD + \ + HEAPBUF_CMD_NOS - 1), + + SHAREDREGION_BASE_CMD = 50, + SHAREDREGION_END_CMD = (SHAREDREGION_BASE_CMD + \ + SHAREDREGION_CMD_NOS - 1), + + GATEPETERSON_BASE_CMD = 70, + GATEPETERSON_END_CMD = (GATEPETERSON_BASE_CMD + \ + GATEPETERSON_CMD_NOS - 1), + + LISTMP_SHAREDMEMORY_BASE_CMD = 90, + LISTMP_SHAREDMEMORY_END_CMD = (LISTMP_SHAREDMEMORY_BASE_CMD + \ + LISTMP_SHAREDMEMORY_CMD_NOS - 1), + + MESSAGEQ_BASE_CMD = 110, + MESSAGEQ_END_CMD = (MESSAGEQ_BASE_CMD + \ + MESSAGEQ_CMD_NOS - 1), + + MESSAGEQ_TRANSPORTSHM_BASE_CMD = 130, + MESSAGEQ_TRANSPORTSHM_END_CMD = (MESSAGEQ_TRANSPORTSHM_BASE_CMD + \ + MESSAGEQ_TRANSPORTSHM_CMD_NOS - 1), + + NAMESERVERREMOTENOTIFY_BASE_CMD = 160, + NAMESERVERREMOTENOTIFY_END_CMD = (NAMESERVERREMOTENOTIFY_BASE_CMD + \ + NAMESERVERREMOTENOTIFY_CMD_NOS - 1), + + SYSMGR_BASE_CMD = 170, + SYSMGR_END_CMD = (SYSMGR_BASE_CMD + \ + SYSMGR_CMD_NOS - 1), + + SYSMEMMGR_BASE_CMD = 180, + SYSMEMMGR_END_CMD = (SYSMEMMGR_BASE_CMD + \ + SYSMEMMGR_CMD_NOS - 1) +}; + +int ipc_ioc_router(u32 cmd, ulong arg); + +#endif /* _IPC_IOCTL_H */ diff --git a/arch/arm/plat-omap/include/syslink/listmp.h b/arch/arm/plat-omap/include/syslink/listmp.h new file mode 100644 index 000000000000..536f1804da91 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/listmp.h @@ -0,0 +1,267 @@ +/* + * listmp.h + * + * The listmp module defines the shared memory doubly linked list. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _LISTMP_H_ +#define _LISTMP_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> +/*#include <heap.h>*/ + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/*! + * @def LISTMP_MODULEID + * @brief Unique module ID. + */ +#define LISTMP_MODULEID (0xa413) + +/*! + * @def LISTMP_ERRORCODEBASE + * @brief Error code base for ListMP. + */ +#define LISTMP_ERRORCODEBASE (LISTMP_MODULEID << 12) + +/*! + * @def LISTMP_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define LISTMP_MAKE_FAILURE(x) ((int)(0x80000000 \ + + (LISTMP_ERRORCODEBASE + (x)))) + +/*! + * @def LISTMP_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define LISTMP_MAKE_SUCCESS(x) (LISTMP_ERRORCODEBASE + (x)) + +/*! + * @def LISTMP_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define LISTMP_E_INVALIDARG LISTMP_MAKE_FAILURE(1) + +/*! + * @def LISTMP_E_MEMORY + * @brief Memory allocation failed. + */ +#define LISTMP_E_MEMORY LISTMP_MAKE_FAILURE(2) + +/*! + * @def LISTMP_E_BUSY + * @brief The name is already registered or not. + */ +#define LISTMP_E_BUSY LISTMP_MAKE_FAILURE(3) + +/*! + * @def LISTMP_E_FAIL + * @brief Generic failure. + */ +#define LISTMP_E_FAIL LISTMP_MAKE_FAILURE(4) + +/*! + * @def LISTMP_E_NOTFOUND + * @brief Name not found in the nameserver. + */ +#define LISTMP_E_NOTFOUND LISTMP_MAKE_FAILURE(5) + +/*! + * @def LISTMP_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define LISTMP_E_INVALIDSTATE LISTMP_MAKE_FAILURE(6) + +/*! + * @def LISTMP_E_OSFAILURE + * @brief Failure in OS call. + */ +#define LISTMP_E_OSFAILURE LISTMP_MAKE_FAILURE(7) + +/*! + * @def LISTMP_SUCCESS + * @brief Operation successful. + */ +#define LISTMP_SUCCESS LISTMP_MAKE_SUCCESS(0) + +/*! + * @def LISTMP_S_ALREADYSETUP + * @brief The LISTMP module has already been setup in this process. + */ +#define LISTMP_S_ALREADYSETUP LISTMP_MAKE_SUCCESS(1) + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/*! + * @brief Enum defining types of list for the ListMP module. + */ +enum listmp_type { + listmp_type_SHARED = 0, + /*!< List in shared memory */ + listmp_type_FAST = 1 + /*!< Hardware Queue */ +}; + +/*! + * @brief Structure defining config parameters for the ListMP module. + */ +struct listmp_config { + u32 max_name_len; + /*!< Maximum length of name */ + bool use_name_server; + /*!< Whether to have this module use the NameServer or not. If the + * NameServer is not needed, set this configuration parameter to false. + * This informs ListMPSharedMemory not to pull in the NameServer module + * In this case, all names passed into create and open are ignored. + */ +}; + +/*! + * @brief Structure defining list element for the ListMP. + */ +struct listmp_elem { + volatile struct listmp_elem *next; + volatile struct listmp_elem *prev; +}; + +/*! + * @brief Structure defining config parameters for the ListMP instances. + */ +struct listmp_params { + bool cache_flag; + /*!< Set to 1 by the open() call. No one else should touch this! */ + struct mutex *gate; + /*!< Lock used for critical region management of the list */ + void *shared_addr; + /*!< shared memory address */ + u32 shared_addr_size; + /*!< shared memory size */ + char *name; + /*!< Name of the object */ + int resource_id; + /*!< + * resourceId Specifies the resource id number. + * Parameter is used only when type is set to Fast List + */ + enum listmp_type list_type ; + /*!< Type of list */ +}; + + +/* ============================================================================= + * Forward declarations + * ============================================================================= + */ +/*! + * @brief Structure defining config parameters for the ListMPSharedMemory. + */ +struct listmp_object { + bool (*empty)(void *listmp_handle); + /* Function to check if list is empty */ + void *(*get_head)(void *listmp_handle); + /* Function to get head element from list */ + void *(*get_tail)(void *listmp_handle); + /* Function to get tail element from list */ + int (*put_head)(void *listmp_handle, struct listmp_elem *elem); + /* Function to put head element into list */ + int (*put_tail)(void *listmp_handle, struct listmp_elem *elem); + /* Function to put tail element into list */ + int (*insert)(void *listmp_handle, struct listmp_elem *elem, + struct listmp_elem *curElem); + /* Function to insert element into list */ + int (*remove)(void *listmp_handle, struct listmp_elem *elem); + /* Function to remove element from list */ + void *(*next)(void *listmp_handle, struct listmp_elem *elem); + /* Function to traverse to next element in list */ + void *(*prev)(void *listmp_handle, struct listmp_elem *elem); + /* Function to traverse to prev element in list */ + void *obj; + /*!< Handle to ListMP */ + enum listmp_type list_type; + /* Type of list */ +}; + +/* + * Function initializes listmp parameters + */ +void listmp_params_init(void *listmp_handle, + struct listmp_params *params); + +/* + * Function to get shared memory requirement for the module + */ +int listmp_shared_memreq(struct listmp_params *params); + +/* ============================================================================= + * Functions to create instance of a list + * ============================================================================= + */ +/* Function to create an instance of ListMP */ +void *listmp_create(struct listmp_params *params); + +/* Function to delete an instance of ListMP */ +int listmp_delete(void **listmp_handle_ptr); + +/* ============================================================================= + * Functions to open/close handle to list instance + * ============================================================================= + */ +/* Function to open a previously created instance */ +int listmp_open(void **listmp_handle_ptr, struct listmp_params *params); + +/* Function to close a previously opened instance */ +int listmp_close(void *listmp_handle); + +/* ============================================================================= + * Function pointer types for list operations + * ============================================================================= + */ +/* Function to check if list is empty */ +bool listmp_empty(void *listmp_handle); + +/* Function to get head element from list */ +void *listmp_get_head(void *listmp_handle); + +/* Function to get tail element from list */ +void *listmp_get_tail(void *listmp_handle); + +/* Function to put head element into list */ +int listmp_put_head(void *listmp_handle, struct listmp_elem *elem); + +/* Function to put tail element into list */ +int listmp_put_tail(void *listmp_handle, struct listmp_elem *elem); + +/* Function to insert element into list */ +int listmp_insert(void *listmp_handle, struct listmp_elem *elem, + struct listmp_elem *curElem); + +/* Function to traverse to remove element from list */ +int listmp_remove(void *listmp_handle, struct listmp_elem *elem); + +/* Function to traverse to next element in list */ +void *listmp_next(void *listmp_handle, struct listmp_elem *elem); + +/* Function to traverse to prev element in list */ +void *listmp_prev(void *listmp_handle, struct listmp_elem *elem); + +#endif /* _LISTMP_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/listmp_sharedmemory.h b/arch/arm/plat-omap/include/syslink/listmp_sharedmemory.h new file mode 100644 index 000000000000..c6fd1629728e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/listmp_sharedmemory.h @@ -0,0 +1,289 @@ +/* + * listmp_sharedmemory.c + * + * The listmp_sharedmemory is a double linked-list based module designed to be + * used in a multi-processor environment. It is designed to provide a means + * of communication between different processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _LISTMP_SHAREDMEMORY_H_ +#define _LISTMP_SHAREDMEMORY_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ + +/* Other headers */ +#include <listmp.h> + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/*! + * @def LISTMPSHAREDMEMORY_MODULEID + * @brief Unique module ID. + */ +#define LISTMPSHAREDMEMORY_MODULEID (0xDD3C) + +/*! + * @def LISTMPSHAREDMEMORY_ERRORCODEBASE + * @brief Error code base for ListMPSharedMemory. + */ +#define LISTMPSHAREDMEMORY_ERRORCODEBASE \ + (LISTMPSHAREDMEMORY_MODULEID << 12) + +/*! + * @def LISTMPSHAREDMEMORY_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define LISTMPSHAREDMEMORY_MAKE_FAILURE(x) \ + ((int) (0x80000000 \ + + (LISTMPSHAREDMEMORY_ERRORCODEBASE \ + + (x)))) + +/*! + * @def LISTMPSHAREDMEMORY_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define LISTMPSHAREDMEMORY_MAKE_SUCCESS(x) \ + (LISTMPSHAREDMEMORY_ERRORCODEBASE + (x)) + +/*! + * @def LISTMPSHAREDMEMORY_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define LISTMPSHAREDMEMORY_E_INVALIDARG \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(1) + +/*! + * @def LISTMPSHAREDMEMORY_E_MEMORY + * @brief Memory allocation failed. + */ +#define LISTMPSHAREDMEMORY_E_MEMORY \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(2) + +/*! + * @def LISTMPSHAREDMEMORY_E_FAIL + * @brief Generic failure. + */ +#define LISTMPSHAREDMEMORY_E_FAIL \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(3) + +/*! + * @def LISTMPSHAREDMEMORY_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define LISTMPSHAREDMEMORY_E_INVALIDSTATE \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(4) + +/*! + * @def LISTMPSHAREDMEMORY_E_OSFAILURE + * @brief Failure in OS call. + */ +#define LISTMPSHAREDMEMORY_E_OSFAILURE \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(5) + +/*! + * @def LISTMPSHAREDMEMORY_E_NOTONWER + * @brief Instance is not created on this processor. + */ +#define LISTMPSHAREDMEMORY_E_NOTOWNER \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(6) + +/*! + * @def LISTMPSHAREDMEMORY_E_REMOTEACTIVE + * @brief Remote opener of the instance has not closed the instance. + */ +#define LISTMPSHAREDMEMORY_E_REMOTEACTIVE \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(7) + +/*! + * @def LISTMPSHAREDMEMORY_E_INUSE + * @brief Indicates that the instance is in use.. + */ +#define LISTMPSHAREDMEMORY_E_INUSE \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(8) + +/*! + * @def LISTMPSHAREDMEMORY_E_NOTFOUND + * @brief name not found in the nameserver. + */ +#define LISTMPSHAREDMEMORY_E_NOTFOUND \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(9) + +/*! + * @def LISTMPSHAREDMEMORY_E_NOTCREATED + * @brief Instance is not created yet + */ +#define LISTMPSHAREDMEMORY_E_NOTCREATED \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(10) + +/*! + * @def LISTMPSHAREDMEMORY_E_VERSION + * @brief Version mismatch error. + */ +#define LISTMPSHAREDMEMORY_E_VERSION \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(11) + +/*! + * @def LISTMPSHAREDMEMORY_E_BUSY + * @brief the name is already registered or not. + */ +#define LISTMPSHAREDMEMORY_E_BUSY \ + LISTMPSHAREDMEMORY_MAKE_FAILURE(12) + + +/*! + * @def LISTMPSHAREDMEMORY_SUCCESS + * @brief Operation successful. + */ +#define LISTMPSHAREDMEMORY_SUCCESS \ + LISTMPSHAREDMEMORY_MAKE_SUCCESS(0) + +/*! + * @def LISTMPSHAREDMEMORY_S_ALREADYSETUP + * @brief The LISTMPSHAREDMEMORY module has already been setup in this + * process. + */ +#define LISTMPSHAREDMEMORY_S_ALREADYSETUP \ + LISTMPSHAREDMEMORY_MAKE_SUCCESS(1) + +/*! + * @def listmp_sharedmemory_CREATED + * @brief Creation of list succesful. +*/ +#define LISTMP_SHAREDMEMORY_CREATED (0x12181964) + +/*! + * @def LISTMP_SHAREDMEMORY_VERSION + * @brief Version. + */ +#define LISTMP_SHAREDMEMORY_VERSION (1) + +/* ============================================================================= + * Structure definitions + * ============================================================================= + */ +/*! + * @brief Structure defining config parameters for the ListMP instances. + */ +#define listmp_sharedmemory_params struct listmp_params + + +/*! @brief Forward declaration of structure defining object for the + * ListMPSharedMemory. + */ +/*! + * @brief Object for the ListMPSharedMemory Handle + */ +#define listmp_sharedmemory_object struct listmp_object + +/*! + * @brief Handle for the ListMPSharedMemory + */ +#define listmp_sharedmemory_handle void * + +/* ============================================================================= + * Functions to create the module + * ============================================================================= + */ +/* Function to get configuration parameters to setup + * the ListMPSharedMemory module. + */ +int listmp_sharedmemory_get_config(struct listmp_config *cfgParams); + +/* Function to setup the ListMPSharedMemory module. */ +int listmp_sharedmemory_setup(struct listmp_config *config) ; + +/* Function to destroy the ListMPSharedMemory module. */ +int listmp_sharedmemory_destroy(void); + +/* ============================================================================= + * Functions to create instance of a list + * ============================================================================= + */ +/* Function to create an instance of ListMP */ +listmp_sharedmemory_handle listmp_sharedmemory_create + (listmp_sharedmemory_params *params); + +/* Function to delete an instance of ListMP */ +int listmp_sharedmemory_delete(listmp_sharedmemory_handle *listMPHandlePtr); + +/* ============================================================================= + * Functions to open/close handle to list instance + * ============================================================================= + */ +/* + * Initialize this config-params structure with supplier-specified + * defaults before instance creation. + */ +void listmp_sharedmemory_params_init(listmp_sharedmemory_handle handle, + listmp_sharedmemory_params *params); + +/* Function to open a previously created instance */ +int listmp_sharedmemory_open(listmp_sharedmemory_handle *listMpHandlePtr, + listmp_sharedmemory_params *params); + +/* Function to close a previously opened instance */ +int listmp_sharedmemory_close(listmp_sharedmemory_handle listMPHandle); + +/* ============================================================================= + * Functions for list operations + * ============================================================================= + */ +/* Function to check if list is empty */ +bool listmp_sharedmemory_empty(listmp_sharedmemory_handle listMPHandle); + +/* Function to get head element from list */ +void *listmp_sharedmemory_get_head(listmp_sharedmemory_handle listMPHandle); + +/* Function to get tail element from list */ +void *listmp_sharedmemory_get_tail(listmp_sharedmemory_handle listMPHandle); + +/* Function to put head element into list */ +int listmp_sharedmemory_put_head(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem); + +/* Function to put tail element into list */ +int listmp_sharedmemory_put_tail(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem); + +/* Function to insert element into list */ +int listmp_sharedmemory_insert(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem, + struct listmp_elem *curElem); + +/* Function to traverse to remove element from list */ +int listmp_sharedmemory_remove(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem); + +/* Function to traverse to next element in list */ +void *listmp_sharedmemory_next(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem); + +/* Function to traverse to prev element in list */ +void *listmp_sharedmemory_prev(listmp_sharedmemory_handle listMPHandle, + struct listmp_elem *elem); + +/* ============================================================================= + * Functions for shared memory requirements + * ============================================================================= + */ +/* Amount of shared memory required for creation of each instance. */ +int listmp_sharedmemory_shared_memreq( + listmp_sharedmemory_params *params); + +#endif /* _LISTMP_SHAREDMEMORY_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/listmp_sharedmemory_ioctl.h b/arch/arm/plat-omap/include/syslink/listmp_sharedmemory_ioctl.h new file mode 100644 index 000000000000..42fc4d6edd24 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/listmp_sharedmemory_ioctl.h @@ -0,0 +1,258 @@ +/* + * listmp_sharedmemory_ioctl.h + * + * Definitions of listmp_sharedmemory driver types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _LISTMP_SHAREDMEMORY_IOCTL_H_ +#define _LISTMP_SHAREDMEMORY_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <listmp_sharedmemory.h> +#include <sharedregion.h> + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* Base command ID for listmp_sharedmemory */ +#define LISTMP_SHAREDMEMORY_IOC_MAGIC IPC_IOC_MAGIC +enum listmp_sharedmemory_drv_cmd { + LISTMP_SHAREDMEMORY_GETCONFIG = LISTMP_SHAREDMEMORY_BASE_CMD, + LISTMP_SHAREDMEMORY_SETUP, + LISTMP_SHAREDMEMORY_DESTROY, + LISTMP_SHAREDMEMORY_PARAMS_INIT, + LISTMP_SHAREDMEMORY_CREATE, + LISTMP_SHAREDMEMORY_DELETE, + LISTMP_SHAREDMEMORY_OPEN, + LISTMP_SHAREDMEMORY_CLOSE, + LISTMP_SHAREDMEMORY_ISEMPTY, + LISTMP_SHAREDMEMORY_GETHEAD, + LISTMP_SHAREDMEMORY_GETTAIL, + LISTMP_SHAREDMEMORY_PUTHEAD, + LISTMP_SHAREDMEMORY_PUTTAIL, + LISTMP_SHAREDMEMORY_INSERT, + LISTMP_SHAREDMEMORY_REMOVE, + LISTMP_SHAREDMEMORY_NEXT, + LISTMP_SHAREDMEMORY_PREV, + LISTMP_SHAREDMEMORY_SHAREDMEMREQ +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for listmp_sharedmemory + * ---------------------------------------------------------------------------- + */ +/* Command for listmp_sharedmemory_get_config */ +#define CMD_LISTMP_SHAREDMEMORY_GETCONFIG \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_GETCONFIG, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_setup */ +#define CMD_LISTMP_SHAREDMEMORY_SETUP \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_SETUP, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_destroy */ +#define CMD_LISTMP_SHAREDMEMORY_DESTROY \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_DESTROY, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_params_init */ +#define CMD_LISTMP_SHAREDMEMORY_PARAMS_INIT \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_PARAMS_INIT, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_create */ +#define CMD_LISTMP_SHAREDMEMORY_CREATE \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_CREATE, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_delete */ +#define CMD_LISTMP_SHAREDMEMORY_DELETE \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_DELETE, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_open */ +#define CMD_LISTMP_SHAREDMEMORY_OPEN \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_OPEN, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_close */ +#define CMD_LISTMP_SHAREDMEMORY_CLOSE \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_CLOSE, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_is_empty */ +#define CMD_LISTMP_SHAREDMEMORY_ISEMPTY \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_ISEMPTY, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_get_head */ +#define CMD_LISTMP_SHAREDMEMORY_GETHEAD \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_GETHEAD, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_get_tail */ +#define CMD_LISTMP_SHAREDMEMORY_GETTAIL \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_GETTAIL, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_put_head */ +#define CMD_LISTMP_SHAREDMEMORY_PUTHEAD \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_PUTHEAD, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_put_tail */ +#define CMD_LISTMP_SHAREDMEMORY_PUTTAIL \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_PUTTAIL, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_insert */ +#define CMD_LISTMP_SHAREDMEMORY_INSERT \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_INSERT, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_remove */ +#define CMD_LISTMP_SHAREDMEMORY_REMOVE \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_REMOVE, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_next */ +#define CMD_LISTMP_SHAREDMEMORY_NEXT \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_NEXT, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_prev */ +#define CMD_LISTMP_SHAREDMEMORY_PREV \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_PREV, \ + struct listmp_sharedmemory_cmd_args) + +/* Command for listmp_sharedmemory_shared_memreq */ +#define CMD_LISTMP_SHAREDMEMORY_SHAREDMEMREQ \ + _IOWR(LISTMP_SHAREDMEMORY_IOC_MAGIC, LISTMP_SHAREDMEMORY_SHAREDMEMREQ, \ + struct listmp_sharedmemory_cmd_args) + +/* Command arguments for listmp_sharedmemory */ +struct listmp_sharedmemory_cmd_args { + union { + struct { + void *listmp_handle; + struct listmp_params *params; + } params_init; + + struct { + struct listmp_config *config; + } get_config; + + struct { + struct listmp_config *config; + } setup; + + struct { + void *listmp_handle; + struct listmp_params *params; + u32 name_len; + u32 shared_addr_srptr; + void *knl_gate; + } create; + + struct { + void *listmp_handle; + } delete_listmp; + + struct { + void *listmp_handle; + struct listmp_params *params; + u32 name_len; + u32 shared_addr_srptr; + void *knl_gate; + } open; + + struct { + void *listmp_handle; + } close; + + struct { + void *listmp_handle; + bool is_empty; + } is_empty; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + } get_head; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + } get_tail; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + } put_head; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + } put_tail; + + struct { + void *listmp_handle; + u32 *new_elem_srptr; + u32 *cur_elem_srptr; + } insert; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + } remove; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + u32 *next_elem_srptr ; + } next; + + struct { + void *listmp_handle; + u32 *elem_srptr ; + u32 *prev_elem_srptr ; + } prev; + + struct { + void *listmp_handle; + struct listmp_params *params; + u32 bytes; + } shared_memreq; + } args; + + int api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for listmp_sharedmemory module + * ---------------------------------------------------------------------------- + */ +/* + * ioctl interface function for listmp_sharedmemory + */ +int listmp_sharedmemory_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _LISTMP_SHAREDMEMORY_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq.h b/arch/arm/plat-omap/include/syslink/messageq.h new file mode 100644 index 000000000000..90ba6f070048 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq.h @@ -0,0 +1,464 @@ +/* + * messageq.h + * + * The MessageQ module supports the structured sending and receiving of + * variable length messages. This module can be used for homogeneous or + * heterogeneous multi-processor messaging. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_H_ +#define _MESSAGEQ_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> + +/* Syslink headers */ +#include <listmp.h> +#include <messageq_transportshm.h> + + +/*! + * @def MESSAGEQ_MODULEID + * @brief Unique module ID. + */ +#define MESSAGEQ_MODULEID (0xded2) + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ + +/*! + * @def MESSAGEQ_STATUSCODEBASE + * @brief Error code base for MessageQ. + */ +#define MESSAGEQ_STATUSCODEBASE (MESSAGEQ_MODULEID << 12) + +/*! + * @def MESSAGEQ_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define MESSAGEQ_MAKE_FAILURE(x) ((int) (0x80000000 + \ + (MESSAGEQ_STATUSCODEBASE + \ + (x)))) + +/*! + * @def MESSAGEQ_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define MESSAGEQ_MAKE_SUCCESS(x) (MESSAGEQ_STATUSCODEBASE + (x)) + +/*! + * @def MESSAGEQ_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define MESSAGEQ_E_INVALIDARG MESSAGEQ_MAKE_FAILURE(1) + +/*! + * @def MESSAGEQ_E_MEMORY + * @brief Memory allocation failed. + */ +#define MESSAGEQ_E_MEMORY MESSAGEQ_MAKE_FAILURE(2) + +/*! + * @def MESSAGEQ_E_BUSY + * @brief the name is already registered or not. + */ +#define MESSAGEQ_E_BUSY MESSAGEQ_MAKE_FAILURE(3) + +/*! + * @def MESSAGEQ_E_FAIL + * @brief Generic failure. + */ +#define MESSAGEQ_E_FAIL MESSAGEQ_MAKE_FAILURE(4) + +/*! + * @def MESSAGEQ_E_NOTFOUND + * @brief name not found in the nameserver. + */ +#define MESSAGEQ_E_NOTFOUND MESSAGEQ_MAKE_FAILURE(5) + +/*! + * @def MESSAGEQ_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define MESSAGEQ_E_INVALIDSTATE MESSAGEQ_MAKE_FAILURE(6) + +/*! + * @def MESSAGEQ_E_NOTONWER + * @brief Instance is not created on this processor. + */ +#define MESSAGEQ_E_NOTONWER MESSAGEQ_MAKE_FAILURE(7) + +/*! + * @def MESSAGEQ_E_REMOTEACTIVE + * @brief Remote opener of the instance has not closed the instance. + */ +#define MESSAGEQ_E_REMOTEACTIVE MESSAGEQ_MAKE_FAILURE(8) + +/*! + * @def MESSAGEQ_E_INUSE + * @brief Indicates that the instance is in use.. + */ +#define MESSAGEQ_E_INUSE MESSAGEQ_MAKE_FAILURE(9) + +/*! + * @def MESSAGEQ_E_INVALIDCONTEXT + * @brief Indicates that the api is called with wrong handle + */ +#define MESSAGEQ_E_INVALIDCONTEXT MESSAGEQ_MAKE_FAILURE(10) + +/*! + * @def MESSAGEQ_E_INVALIDMSG + * @brief Indicates that an invalid msg has been specified + * + */ +#define MESSAGEQ_E_INVALIDMSG MESSAGEQ_MAKE_FAILURE(11) + +/*! + * @def MESSAGEQ_E_INVALIDHEAPID + * @brief Indicates that an invalid heap has been specified + */ +#define MESSAGEQ_E_INVALIDHEAPID MESSAGEQ_MAKE_FAILURE(12) + +/*! + * @def MESSAGEQ_E_INVALIDPROCID + * @brief Indicates that an invalid proc id has been specified + */ +#define MESSAGEQ_E_INVALIDPROCID MESSAGEQ_MAKE_FAILURE(13) + +/*! + * @def MESSAGEQ_E_MAXREACHED + * @brief Indicates that all message queues are taken + */ +#define MESSAGEQ_E_MAXREACHED MESSAGEQ_MAKE_FAILURE(14) + +/*! + * @def MESSAGEQ_E_UNREGISTERHEAPID + * @brief Indicates that heap id has not been registered + */ +#define MESSAGEQ_E_UNREGISTERHEAPID MESSAGEQ_MAKE_FAILURE(15) + +/*! + * @def MESSAGEQ_E_CANNOTFREESTATICMSG + * @brief Indicates that static msg cannot be freed + */ +#define MESSAGEQ_E_CANNOTFREESTATICMSG MESSAGEQ_MAKE_FAILURE(16) + +/*! + * @def MESSAGEQ_E_HEAPIDINVALID + * @brief Indicates that the heap id is invalid + */ +#define MESSAGEQ_E_HEAPIDINVALID MESSAGEQ_MAKE_FAILURE(17) + +/*! + * @def MESSAGEQ_E_PROCIDINVALID + * @brief Indicates that the proc id is invalid + */ +#define MESSAGEQ_E_PROCIDINVALID MESSAGEQ_MAKE_FAILURE(18) + +/*! + * @def MESSAGEQ_E_OSFAILURE + * @brief Failure in OS call. + */ +#define MESSAGEQ_E_OSFAILURE MESSAGEQ_MAKE_FAILURE(19) + +/*! + * @def MESSAGEQ_E_ALREADYEXISTS + * @brief Specified entity already exists + */ +#define MESSAGEQ_E_ALREADYEXISTS MESSAGEQ_MAKE_FAILURE(20) + +/*! + * @def MESSAGEQ_E_TIMEOUT + * @brief Timeout while attempting to get a message + */ +#define MESSAGEQ_E_TIMEOUT MESSAGEQ_MAKE_FAILURE(21) + +/*! + * @def MESSAGEQ_SUCCESS + * @brief Operation successful. + */ +#define MESSAGEQ_SUCCESS MESSAGEQ_MAKE_SUCCESS(0) + +/*! + * @def MESSAGEQ_S_ALREADYSETUP + * @brief The MESSAGEQ module has already been setup in this process. + */ +#define MESSAGEQ_S_ALREADYSETUP MESSAGEQ_MAKE_SUCCESS(1) + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/*! + * @brief Mask to extract version setting + */ +#define MESSAGEQ_HEADERVERSION 0x2000u + +/*! + * @brief Mask to extract priority setting + */ +#define MESSAGEQ_PRIORITYMASK 0x3u + +/*! + * @brief Mask to extract priority setting + */ +#define MESSAGEQ_TRANSPORTPRIORITYMASK 0x01u + +/*! + * Mask to extract version setting + */ +#define MESSAGEQ_VERSIONMASK 0xE000; + +/*! + * Used as the timeout value to specify wait forever + */ +#define MESSAGEQ_FOREVER (~((u32) 0)) + +/*! + * Invalid message id + */ +#define MESSAGEQ_INVALIDMSGID 0xFFFF + +/*! + * Invalid message queue + */ +#define MESSAGEQ_INVALIDMESSAGEQ 0xFFFF + +/*! + * Indicates that if maximum number of message queues are already created, + * should allow growth to create additional Message Queue. + */ +#define MESSAGEQ_ALLOWGROWTH (~((u32) 0)) + +/*! + * Number of types of priority queues for each transport + */ +#define MESSAGEQ_NUM_PRIORITY_QUEUES 2 + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ +/*! + * Message priority + */ +enum messageq_priority { + MESSAGEQ_NORMALPRI = 0, + /*!< Normal priority message */ + MESSAGEQ_HIGHPRI = 1, + /*!< High priority message */ + MESSAGEQ_RESERVEDPRI = 2, + /*!< Reserved value for message priority */ + MESSAGEQ_URGENTPRI = 3 + /*!< Urgent priority message */ +}; + +/*! Structure which defines the first field in every message */ +struct msgheader { + u32 reserved0; + /*!< Reserved field */ + u32 reserved1; + /*!< Reserved field */ + u32 msg_size; + /*!< Size of the message (including header) */ + u16 flags; + /*!< Flags */ + u16 msg_id; + /*!< Maximum length for Message queue names */ + u16 dst_id; + /*!< Maximum length for Message queue names */ + u16 dst_proc; + /*!< Maximum length for Message queue names */ + u16 reply_id; + /*!< Maximum length for Message queue names */ + u16 reply_proc; + /*!< Maximum length for Message queue names */ + u16 src_proc; + /*!< Maximum length for Message queue names */ + u16 heap_id; + /*!< Maximum length for Message queue names */ + u32 reserved; + /*!< Reserved field */ +}; +/*! Structure which defines the first field in every message */ +#define messageq_msg struct msgheader * +/*typedef struct msgheader *messageq_msg;*/ + + +/*! + * @brief Structure defining config parameters for the MessageQ Buf module. + */ +struct messageq_config { + u16 num_heaps; + /*! + * Number of heapIds in the system + * + * This allows MessageQ to pre-allocate the heaps table. + * The heaps table is used when registering heaps. + * + * The default is 1 since generally all systems need at least + * one heap. + * + * There is no default heap, so unless the system is only using + * staticMsgInit, the application must register a heap. + */ + + u32 max_runtime_entries; + /*! + * Maximum number of MessageQs that can be dynamically created + */ + + struct mutex *name_table_gate; + /*! + * Gate used to make the name table thread safe. If NULL is passed, gate + * will be created internally. + */ + + u32 max_name_len; + /*! + * Maximum length for Message queue names + */ +}; + +struct messageq_params { + u32 reserved; + /*!< No parameters required currently. Reserved field. */ + u32 max_name_len; + /*!< Maximum length for Message queue names */ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Functions to get the configuration for messageq setup */ +void messageq_get_config(struct messageq_config *cfg); + +/* Function to setup the MessageQ module. */ +int messageq_setup(const struct messageq_config *cfg); + +/* Function to destroy the MessageQ module. */ +int messageq_destroy(void); + +/* Initialize this config-params structure with supplier-specified + * defaults before instance creation. + */ +void messageq_params_init(void *messageq_handle, + struct messageq_params *params); + +/* Create a message queue */ +void *messageq_create(char *name, const struct messageq_params *params); + +/* Deletes a instance of MessageQ module. */ +int messageq_delete(void **messageq_handleptr); + +/* Allocates a message from the heap */ +messageq_msg messageq_alloc(u16 heapId, u32 size); + +/* Frees a message back to the heap */ +int messageq_free(messageq_msg msg); + +/* Open a message queue */ +int messageq_open(char *name, u32 *queue_id); + +/* Close an opened message queue handle */ +void messageq_close(u32 *queue_id); + +/* Initializes a message not obtained from MessageQ_alloc */ +void messageq_static_msg_init(messageq_msg msg, u32 size); + +/* Place a message onto a message queue */ +int messageq_put(u32 queueId, messageq_msg msg); + +/* Gets a message for a message queue and blocks if the queue is empty */ +int messageq_get(void *messageq_handle, messageq_msg *msg, + u32 timeout); + +/* Register a heap with MessageQ */ +int messageq_register_heap(void *heap_handle, u16 heap_id); + +/* Unregister a heap with MessageQ */ +int messageq_unregister_heap(u16 heapId); + +/* Returns the number of messages in a message queue */ +int messageq_count(void *messageq_handle); + +/* Set the destination queue of the message. */ +void messageq_set_reply_queue(void *messageq_handle, messageq_msg msg); + +/* Get the queue Id of the message. */ +u32 messageq_get_queue_id(void *messageq_handle); + +/* Get the proc Id of the message. */ +u16 messageq_get_proc_id(void *messageq_handle); + +/* + * Functions to set Message properties + */ +/*! + * @brief Returns the MessageQ_Queue handle of the destination + * message queue for the specified message. + */ +u32 messageq_get_dst_queue(messageq_msg msg); + +/*! + * @brief Returns the message ID of the specified message. + */ +u16 messageq_get_msg_id(messageq_msg msg); + +/*! + * @brief Returns the size of the specified message. + */ +u32 messageq_get_msg_size(messageq_msg msg); + +/*! + * @brief Gets the message priority of a message + */ +u32 messageq_get_msg_pri(messageq_msg msg); + +/*! + * @brief Returns the MessageQ_Queue handle of the destination + * message queue for the specified message. + */ +u32 messageq_get_reply_queue(messageq_msg msg); + +/*! + * @brief Sets the message ID in the specified message. + */ +void messageq_set_msg_id(messageq_msg msg, u16 msg_id); +/*! + * @brief Sets the message priority in the specified message. + */ +void messageq_set_msg_pri(messageq_msg msg, u32 priority); + +/* ============================================================================= + * APIs called internally by MessageQ transports + * ============================================================================= + */ +/* Register a transport with MessageQ */ +int messageq_register_transport(void *messageq_transportshm_handle, + u16 proc_id, u32 priority); + +/* Unregister a transport with MessageQ */ +int messageq_unregister_transport(u16 proc_id, u32 priority); + + +#endif /* _MESSAGEQ_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq_ioctl.h b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h new file mode 100644 index 000000000000..2f8424c21d7e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq_ioctl.h @@ -0,0 +1,237 @@ +/* + * messageq_ioctl.h + * + * Definitions of messageq driver types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_IOCTL_H_ +#define _MESSAGEQ_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <messageq.h> +#include <heap.h> +#include <sharedregion.h> + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +#define MESSAGEQ_IOC_MAGIC IPC_IOC_MAGIC +enum messageq_drv_cmd { + MESSAGEQ_GETCONFIG = MESSAGEQ_BASE_CMD, + MESSAGEQ_SETUP, + MESSAGEQ_DESTROY, + MESSAGEQ_PARAMS_INIT, + MESSAGEQ_CREATE, + MESSAGEQ_DELETE, + MESSAGEQ_OPEN, + MESSAGEQ_CLOSE, + MESSAGEQ_COUNT, + MESSAGEQ_ALLOC, + MESSAGEQ_FREE, + MESSAGEQ_PUT, + MESSAGEQ_REGISTERHEAP, + MESSAGEQ_UNREGISTERHEAP, + MESSAGEQ_REGISTERTRANSPORT, + MESSAGEQ_UNREGISTERTRANSPORT, + MESSAGEQ_GET +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for messageq + * ---------------------------------------------------------------------------- + */ +/* Base command ID for messageq */ +#define MESSAGEQ_BASE_CMD 0x0 + +/* Command for messageq_get_config */ +#define CMD_MESSAGEQ_GETCONFIG \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GETCONFIG, \ + struct messageq_cmd_args) + +/* Command for messageq_setup */ +#define CMD_MESSAGEQ_SETUP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_SETUP, \ + struct messageq_cmd_args) + +/* Command for messageq_destroy */ +#define CMD_MESSAGEQ_DESTROY \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DESTROY, \ + struct messageq_cmd_args) + +/* Command for messageq_params_init */ +#define CMD_MESSAGEQ_PARAMS_INIT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PARAMS_INIT, \ + struct messageq_cmd_args) + +/* Command for messageq_create */ +#define CMD_MESSAGEQ_CREATE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CREATE, \ + struct messageq_cmd_args) + +/* Command for messageq_delete */ +#define CMD_MESSAGEQ_DELETE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_DELETE, \ + struct messageq_cmd_args) + +/* Command for messageq_open */ +#define CMD_MESSAGEQ_OPEN \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_OPEN, \ + struct messageq_cmd_args) + +/* Command for messageq_close */ +#define CMD_MESSAGEQ_CLOSE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_CLOSE, \ + struct messageq_cmd_args) + +/* Command for messageq_count */ +#define CMD_MESSAGEQ_COUNT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_COUNT, \ + struct messageq_cmd_args) + +/* Command for messageq_alloc */ +#define CMD_MESSAGEQ_ALLOC \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_ALLOC, \ + struct messageq_cmd_args) + +/* Command for messageq_free */ +#define CMD_MESSAGEQ_FREE \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_FREE, \ + struct messageq_cmd_args) + +/* Command for messageq_put */ +#define CMD_MESSAGEQ_PUT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_PUT, \ + struct messageq_cmd_args) + +/* Command for messageq_register_heap */ +#define CMD_MESSAGEQ_REGISTERHEAP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_REGISTERHEAP, \ + struct messageq_cmd_args) + +/* Command for messageq_unregister_heap */ +#define CMD_MESSAGEQ_UNREGISTERHEAP \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_UNREGISTERHEAP, \ + struct messageq_cmd_args) + + +/* Command for messageq_register_transport */ +#define CMD_MESSAGEQ_REGISTERTRANSPORT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_REGISTERTRANSPORT, \ + struct messageq_cmd_args) + + +/* Command for messageq_unregister_transport */ +#define CMD_MESSAGEQ_UNREGISTERTRANSPORT \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_UNREGISTERTRANSPORT, \ + struct messageq_cmd_args) + + +/* Command for messageq_get */ +#define CMD_MESSAGEQ_GET \ + _IOWR(MESSAGEQ_IOC_MAGIC, MESSAGEQ_GET, \ + struct messageq_cmd_args) + +/* Command arguments for messageq */ +struct messageq_cmd_args { + union { + struct { + void *messageq_handle; + struct messageq_params *params; + } params_init; + + struct { + struct messageq_config *config; + } get_config; + + struct { + struct messageq_config *config; + } setup; + + struct { + void *messageq_handle; + char *name; + struct messageq_params *params; + u32 name_len; + u32 queue_id; + } create; + + struct { + void *messageq_handle; + } delete_messageq; + + struct { + char *name; + u32 queue_id; + u32 name_len; + } open; + + struct { + u32 queue_id; + } close; + + struct { + void *messageq_handle; + u32 timeout; + u32 *msg_srptr; + } get; + + struct { + void *messageq_handle; + int count; + } count; + + struct { + u16 heap_id; + u32 size; + u32 *msg_srptr; + } alloc; + + struct { + u32 *msg_srptr; + } free; + + struct { + u32 queue_id; + u32 *msg_srptr; + } put; + + struct { + void *heap_handle; + u16 heap_id; + } register_heap; + + struct { + u16 heap_id; + } unregister_heap; + } args; + + int api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for messageq module + * ---------------------------------------------------------------------------- + */ +/* + * ioctl interface function for messageq + */ +int messageq_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _MESSAGEQ_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq_transportshm.h b/arch/arm/plat-omap/include/syslink/messageq_transportshm.h new file mode 100644 index 000000000000..e2b55f6b0b4d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq_transportshm.h @@ -0,0 +1,283 @@ +/* + * messageq_transportshm.h + * + * MessageQ shared memory based physical transport for + * communication with the remote processor. + * + * This file contains the declarations of types and APIs as part + * of interface of the MessageQ shared memory transport. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_TRANSPORTSHM_H_ +#define _MESSAGEQ_TRANSPORTSHM_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Utilities headers */ +#include <linux/list.h> + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/*! + * @def MESSAGEQ_TRANSPORTSHM_MODULEID + * @brief Unique module ID. + */ +#define MESSAGEQ_TRANSPORTSHM_MODULEID (0x0a7a) + +/* ============================================================================= + * All success and failure codes for the module + * ============================================================================= + */ +/*! + * @def MESSAGEQ_TRANSPORTSHM_STATUSCODEBASE + * @brief Error code base for MessageQ. + */ +#define MESSAGEQ_TRANSPORTSHM_STATUSCODEBASE \ + (MESSAGEQ_TRANSPORTSHM_MODULEID << 12) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(x) ((int) (0x80000000 \ + + (MESSAGEQ_TRANSPORTSHM_STATUSCODEBASE \ + + (x)))) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define MESSAGEQ_TRANSPORTSHM_MAKE_SUCCESS(x) \ + (MESSAGEQ_TRANSPORTSHM_STATUSCODEBASE + (x)) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define MESSAGEQ_TRANSPORTSHM_E_INVALIDARG \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(1) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_INVALIDSIZE + * @brief Invalid shared address size + */ +#define MESSAGEQ_TRANSPORTSHM_E_INVALIDSIZE \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(2) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define MESSAGEQ_TRANSPORTSHM_E_INVALIDSTATE \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(3) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_BADVERSION + * @brief Versions don't match + */ +#define MESSAGEQ_TRANSPORTSHM_E_BADVERSION \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(4) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_FAIL + * @brief General Failure +*/ +#define MESSAGEQ_TRANSPORTSHM_E_FAIL \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(5) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_MEMORY + * @brief Memory allocation failed + */ +#define MESSAGEQ_TRANSPORTSHM_E_MEMORY \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(6) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_OSFAILURE + * @brief Failure in OS call. + */ +#define MESSAGEQ_TRANSPORTSHM_E_OSFAILURE \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(7) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_E_HANDLE + * @brief Invalid handle specified. + */ +#define MESSAGEQ_TRANSPORTSHM_E_HANDLE \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(8) + +/*! + * @def MESSAGEQTRANSPORTSHM_E_NOTSUPPORTED + * @brief The specified operation is not supported. + */ +#define MESSAGEQTRANSPORTSHM_E_NOTSUPPORTED \ + MESSAGEQ_TRANSPORTSHM_MAKE_FAILURE(9) + +/*! + * @def MESSAGEQ_TRANSPORTSHM_SUCCESS + * @brief Operation successful. + */ +#define MESSAGEQ_TRANSPORTSHM_SUCCESS \ + MESSAGEQ_TRANSPORTSHM_MAKE_SUCCESS(0) + +/*! + * @def MESSAGETRANSPORTSHM_S_ALREADYSETUP + * @brief The MESSAGETRANSPORTSHM module has + * already been setup in this process. + */ +#define MESSAGEQ_TRANSPORTSHM_S_ALREADYSETUP \ + MESSAGEQ_TRANSPORTSHM_MAKE_SUCCESS(1) + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ + +/*! + * @brief Structure defining the reason for error function being called + */ +enum MessageQTransportShm_Reason { + MessageQTransportShm_Reason_FAILEDPUT, + /*!< Failed to send the message. */ + MessageQTransportShm_Reason_INTERNALERR, + /*!< An internal error occurred in the transport */ + MessageQTransportShm_Reason_PHYSICALERR, + /*!< An error occurred in the physical link in the transport */ + MessageQTransportShm_Reason_FAILEDALLOC + /*!< Failed to allocate a message. */ +}; + +/*! + * @brief transport error callback function. + * + * First parameter: Why the error function is being called. + * + * Second parameter: Handle of transport that had the error. NULL denotes + * that it is a system error, not a specific transport. + * + * Third parameter: Pointer to the message. This is only valid for + * #MessageQTransportShm_Reason_FAILEDPUT. + * + * Fourth parameter: Transport specific information. Refer to individual + * transports for more details. + */ + +/*! + * @brief Module configuration structure. + */ +struct messageq_transportshm_config { + void (*err_fxn)(enum MessageQTransportShm_Reason reason, + void *handle, + void *msg, + u32 info); + /*!< Asynchronous error function for the transport module */ +}; + +/*! + * @brief Structure defining config parameters for the MessageQ transport + * instances. + */ +struct messageq_transportshm_params { + u32 priority; + /*!< Priority of messages supported by this transport */ + void *gate; + /*!< Gate used for critical region management of the shared memory */ + void *shared_addr; + /*!< Address of the shared memory. The creator must supply the shared + * memory that this will use for maintain shared state information. + */ + u32 shared_addr_size; + /*!< Size of shared region provided. */ + u32 notify_event_no; + /*!< Notify event number to be used by the transport */ + void *notify_driver; + /*!< Notify driver to be used by the transport */ +}; + +/*! + * @brief Structure defining Transport status values + */ +enum messageq_transportshm_status { + messageq_transportshm_status_INIT, + /*!< MessageQ transport Shm instance has not not completed + * initialization. */ + messageq_transportshm_status_UP, + /*!< MessageQ transport Shm instance is up and functional. */ + messageq_transportshm_status_DOWN, + /*!< MessageQ transport Shm instance is down and not functional. */ + messageq_transportshm_status_RESETTING + /*!< MessageQ transport Shm instance was up at one point and is in + * process of resetting. + */ +}; + + +/* ============================================================================= + * APIs called by applications + * ============================================================================= + */ +/* Function to get the default configuration for the MessageQTransportShm + * module. */ +void messageq_transportshm_get_config(struct messageq_transportshm_config *cfg); + +/* Function to setup the MessageQTransportShm module. */ +int messageq_transportshm_setup(const struct messageq_transportshm_config *cfg); + +/* Function to destroy the MessageQTransportShm module. */ +int messageq_transportshm_destroy(void); + +/* Get the default parameters for the NotifyShmDriver. */ +void messageq_transportshm_params_init(void *mqtshm_handle, + struct messageq_transportshm_params *params); + +/* Create an instance of the MessageQTransportShm. */ +void *messageq_transportshm_create(u16 proc_id, + const struct messageq_transportshm_params *params); + +/* Delete an instance of the MessageQTransportShm. */ +int messageq_transportshm_delete(void **mqtshm_handleptr); + +/* Get the shared memory requirements for the MessageQTransportShm. */ +u32 messageq_transportshm_shared_mem_req(const + struct messageq_transportshm_params *params); + +/* Set the asynchronous error function for the transport module */ +void messageq_transportshm_set_err_fxn( + void (*err_fxn)( + enum MessageQTransportShm_Reason reason, + void *handle, + void *msg, + u32 info)); + + +/* ============================================================================= + * APIs called internally by MessageQ module. + * ============================================================================= + */ +/* Put msg to remote list */ +int messageq_transportshm_put(void *mqtshm_handle, void *msg); + +/* Control Function */ +int messageq_transportshm_control(void *mqtshm_handle, u32 cmd, + u32 *cmd_arg); + +/* Get current status of the MessageQTransportShm */ +enum messageq_transportshm_status messageq_transportshm_get_status( + void *mqtshm_handle); + +#endif /* _MESSAGEQ_TRANSPORTSHM_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/messageq_transportshm_ioctl.h b/arch/arm/plat-omap/include/syslink/messageq_transportshm_ioctl.h new file mode 100644 index 000000000000..3790dc0d22e8 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/messageq_transportshm_ioctl.h @@ -0,0 +1,160 @@ +/* + * messageq_transportshm_ioctl.h + * + * Definitions of messageq_transportshm driver types and structures. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _MESSAGEQ_TRANSPORTSHM_IOCTL_H_ +#define _MESSAGEQ_TRANSPORTSHM_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <messageq_transportshm.h> +#include <sharedregion.h> + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* Base command ID for messageq_transportshm */ +#define MESSAGEQ_TRANSPORTSHM_IOC_MAGIC IPC_IOC_MAGIC +enum messageq_transportshm_drv_cmd { + MESSAGEQ_TRANSPORTSHM_GETCONFIG = MESSAGEQ_TRANSPORTSHM_BASE_CMD, + MESSAGEQ_TRANSPORTSHM_SETUP, + MESSAGEQ_TRANSPORTSHM_DESTROY, + MESSAGEQ_TRANSPORTSHM_PARAMS_INIT, + MESSAGEQ_TRANSPORTSHM_CREATE, + MESSAGEQ_TRANSPORTSHM_DELETE, + MESSAGEQ_TRANSPORTSHM_PUT, + MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ, + MESSAGEQ_TRANSPORTSHM_GETSTATUS +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for messageq_transportshm + * ---------------------------------------------------------------------------- + */ +/* Base command ID for messageq_transportshm */ +#define MESSAGEQ_TRANSPORTSHM_BASE_CMD 0x0 + +/* Command for messageq_transportshm_get_config */ +#define CMD_MESSAGEQ_TRANSPORTSHM_GETCONFIG \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \ + MESSAGEQ_TRANSPORTSHM_GETCONFIG, struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_setup */ +#define CMD_MESSAGEQ_TRANSPORTSHM_SETUP \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_SETUP, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_setup */ +#define CMD_MESSAGEQ_TRANSPORTSHM_DESTROY \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_DESTROY, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_destroy */ +#define CMD_MESSAGEQ_TRANSPORTSHM_PARAMS_INIT \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \ + MESSAGEQ_TRANSPORTSHM_PARAMS_INIT, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_create */ +#define CMD_MESSAGEQ_TRANSPORTSHM_CREATE \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_CREATE, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_delete */ +#define CMD_MESSAGEQ_TRANSPORTSHM_DELETE \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_DELETE, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_put */ +#define CMD_MESSAGEQ_TRANSPORTSHM_PUT \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, MESSAGEQ_TRANSPORTSHM_PUT, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_shared_memreq */ +#define CMD_MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \ + MESSAGEQ_TRANSPORTSHM_SHAREDMEMREQ, \ + struct messageq_transportshm_cmd_args) + +/* Command for messageq_transportshm_get_status */ +#define CMD_MESSAGEQ_TRANSPORTSHM_GETSTATUS \ + _IOWR(MESSAGEQ_TRANSPORTSHM_IOC_MAGIC, \ + MESSAGEQ_TRANSPORTSHM_GETSTATUS, struct messageq_transportshm_cmd_args) + +/* Command arguments for messageq_transportshm */ +struct messageq_transportshm_cmd_args { + union { + struct { + struct messageq_transportshm_config *config; + } get_config; + + struct { + struct messageq_transportshm_config *config; + } setup; + + struct { + void *messageq_transportshm_handle; + struct messageq_transportshm_params *params; + } params_init; + + struct { + void *messageq_transportshm_handle; + u16 proc_id; + struct messageq_transportshm_params *params; + u32 shared_addr_srptr; + void *knl_lock_handle; + void *knl_notify_driver; + } create; + + struct { + void *messageq_transportshm_handle; + } delete_transport; + + struct { + void *messageq_transportshm_handle; + u32 *msg_srptr; + } put; + + struct { + void *messageq_transportshm_handle; + enum messageq_transportshm_status status; + } get_status; + + struct { + struct messageq_transportshm_params *params; + u32 bytes; + } shared_memreq; + } args; + + int api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for messageq_transportshm module + * ---------------------------------------------------------------------------- + */ +/* + * ioctl interface function for messageq_transportshm + */ +int messageq_transportshm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _MESSAGEQ_TRANSPORTSHM_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/multiproc.h b/arch/arm/plat-omap/include/syslink/multiproc.h new file mode 100755 index 000000000000..6361bae80d19 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/multiproc.h @@ -0,0 +1,83 @@ +/* +* multiproc.h +* +* Many multi-processor modules have the concept of processor id. multiproc +* centeralizes the processor id management. +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _MULTIPROC_H_ +#define _MULTIPROC_H_ + +#include <linux/types.h> + + +#define VOLATILE volatile + +/* + * Unique module ID + */ +#define MULTIPROC_MODULEID (u16)0xB522 + +/* Macro to define invalid processor id */ +#define MULTIPROC_INVALIDID ((u16)0xFFFF) + +/* + * Maximum number of processors in the system + * OMAP4 has 4 processors in single core. + */ +#define MULTIPROC_MAXPROCESSORS 4 + +/* + * Max name length for a processor name + */ +#define MULTIPROC_MAXNAMELENGTH 32 + +/* + * Configuration structure for multiproc module + */ +struct multiproc_config { + s32 max_processors; /* Max number of procs for particular system */ + char name_list[MULTIPROC_MAXPROCESSORS][MULTIPROC_MAXNAMELENGTH]; + /* Name List for processors in the system */ + u16 id; /* Local Proc ID. This needs to be set before calling any + other APIs */ +}; + +/* ============================================================================= + * APIs + * ============================================================================= + */ + +/* Function to get the default configuration for the multiproc module. */ +void multiproc_get_config(struct multiproc_config *cfg); + +/* Function to setup the multiproc Module */ +s32 multiproc_setup(struct multiproc_config *cfg); + +/* Function to destroy the multiproc module */ +s32 multiproc_destroy(void); + +/* Function to set local processor Id */ +int multiproc_set_local_id(u16 proc_id); + +/* Function to get processor id from processor name. */ +u16 multiproc_get_id(const char *proc_name); + +/* Function to get name from processor id. */ +char *multiproc_get_name(u16 proc_id); + +/* Function to get maximum proc Id in the system. */ +u16 multiproc_get_max_processors(void); + +#endif /* _MULTIPROC_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h new file mode 100755 index 000000000000..0c9780136b02 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/multiproc_ioctl.h @@ -0,0 +1,94 @@ +/* +* multiproc_ioctl.h +* +* This provides the ioctl interface for multiproc module +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _MULTIPROC_IOCTL_H_ +#define _MULTIPROC_IOCTL_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <multiproc.h> + +enum CMD_MULTIPROC { + MULTIPROC_SETUP = MULTIPROC_BASE_CMD, + MULTIPROC_DESTROY, + MULTIPROC_GETCONFIG, + MULTIPROC_SETLOCALID +}; + +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for MultiProc + * ---------------------------------------------------------------------------- + */ + +/* + * Command for multiproc_setup + */ +#define CMD_MULTIPROC_SETUP _IOWR(IPC_IOC_MAGIC, MULTIPROC_SETUP, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_destroy + */ +#define CMD_MULTIPROC_DESTROY _IOWR(IPC_IOC_MAGIC, MULTIPROC_DESTROY, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_get_config + */ +#define CMD_MULTIPROC_GETCONFIG _IOWR(IPC_IOC_MAGIC, MULTIPROC_GETCONFIG, \ + struct multiproc_cmd_args) + +/* + * Command for multiproc_set_local_id + */ +#define CMD_MULTIPROC_SETLOCALID _IOWR(IPC_IOC_MAGIC, MULTIPROC_SETLOCALID, \ + struct multiproc_cmd_args) + +/* + * Command arguments for multiproc + */ +union multiproc_arg { + struct { + struct multiproc_config *config; + } get_config; + + struct { + struct multiproc_config *config; + } setup; + + struct { + u16 id; + } set_local_id; +}; + +/* + * Command arguments for multiproc + */ +struct multiproc_cmd_args { + union multiproc_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for multiproc module + */ +int multiproc_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _MULTIPROC_IOCTL_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver.h b/arch/arm/plat-omap/include/syslink/nameserver.h new file mode 100644 index 000000000000..87265d856d9b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver.h @@ -0,0 +1,131 @@ +/* + * nameserver.h + * + * The nameserver module manages local name/value pairs that + * enables an application and other modules to store and retrieve + * values based on a name. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_H_ +#define _NAMESERVER_H_ + +#include <linux/types.h> +#include <linux/list.h> + +/* + * NAMESERVER_MODULEID + * Unique module ID + */ +#define NAMESERVER_MODULEID (0xF414) + +/* + * Instance config-params object. + */ +struct nameserver_params { + bool check_existing; /* Prevents duplicate entry add in to the table */ + void *gate_handle; /* Lock used for critical region of the table */ + u16 max_name_len; /* Length, in MAUs, of name field */ + u32 max_runtime_entries; + u32 max_value_len; /* Length, in MAUs, of the value field */ + void *table_heap; /* Table is placed into a section on dyn creates */ +}; + +/* + * Function to setup the nameserver module + */ +int nameserver_setup(void); + +/* + * Function to destroy the nameserver module + */ +int nameserver_destroy(void); + +/* + * Function to initialize the parameter structure + */ +int nameserver_params_init(struct nameserver_params *params); + +/* + * Function to initialize the parameter structure + */ +int nameserver_get_params(void *handle, + struct nameserver_params *params); + +/* + * Function to create a name server + */ +void *nameserver_create(const char *name, + const struct nameserver_params *params); + +/* + * Function to delete a name server + */ +int nameserver_delete(void **handle); + +/* + * Function to add a variable length value into the local table + */ +void *nameserver_add(void *handle, const char *name, + void *buffer, u32 length); + +/* + * Function to add a 32 bit value into the local table + */ +void *nameserver_add_uint32(void *handle, + const char *name, u32 value); + +/* + * Function to Retrieve the value portion of a name/value pair + */ +int nameserver_get(void *handle, const char *name, + void *buffer, u32 length, u16 procId[]); + +/* + * Function to get the value portion of a name/value pair from local table + */ +int nameserver_get_local(void *handle, const char *name, + void *buffer, u32 length); + +/* + * Function to removes a value/pair + */ +int nameserver_remove(void *handle, const char *name); + +/* + * Function to Remove an entry from the table + */ +int nameserver_remove_entry(void *nshandle, void *nsentry); + +/* + * Function to handle for a name + */ +void *nameserver_get_handle(const char *name); + +/* + * Function to Match the name + */ +int nameserver_match(void *handle, const char *name, u32 *value); + +/* + * Function to register a remote driver + */ +int nameserver_register_remote_driver(void *handle, u16 proc_id); + +/* + * Function to unregister a remote driver + */ +int nameserver_unregister_remote_driver(u16 proc_id); + +#endif /* _NAMESERVER_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h new file mode 100644 index 000000000000..defb71fae47b --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_ioctl.h @@ -0,0 +1,230 @@ +/* +* nameserver_ioctl.h +* +* This provides the ioctl interface for nameserver module +* +* Copyright (C) 2008-2009 Texas Instruments, Inc. +* +* This package is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. +*/ + +#ifndef _NAMESERVER_IOCTL_H_ +#define _NAMESERVER_IOCTL_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <nameserver.h> + +enum CMD_NAMESERVER { + NAMESERVER_SETUP = NAMESERVER_BASE_CMD, + NAMESERVER_DESTROY, + NAMESERVER_PARAMS_INIT, + NAMESERVER_CREATE, + NAMESERVER_DELETE, + NAMESERVER_ADD, + NAMESERVER_ADDUINT32, + NAMESERVER_GET, + NAMESERVER_GETLOCAL, + NAMESERVER_MATCH, + NAMESERVER_REMOVE, + NAMESERVER_REMOVEENTRY, + NAMESERVER_GETHANDLE, +}; + +/* + * IOCTL command IDs for nameserver + * + */ +/* + * Command for nameserver_setup + */ +#define CMD_NAMESERVER_SETUP _IOWR(IPC_IOC_MAGIC, NAMESERVER_SETUP, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_destroy + */ +#define CMD_NAMESERVER_DESTROY _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_DESTROY, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_params_init + */ +#define CMD_NAMESERVER_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_PARAMS_INIT, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_create + */ +#define CMD_NAMESERVER_CREATE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_CREATE, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_delete + */ +#define CMD_NAMESERVER_DELETE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_DELETE, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_add + */ +#define CMD_NAMESERVER_ADD _IOWR(IPC_IOC_MAGIC, NAMESERVER_ADD, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_addu32 + */ +#define CMD_NAMESERVER_ADDUINT32 _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_ADDUINT32, \ + struct nameserver_cmd_args) +/* + * Command for nameserver_get + */ +#define CMD_NAMESERVER_GET _IOWR(IPC_IOC_MAGIC, NAMESERVER_GET, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_get_local + */ +#define CMD_NAMESERVER_GETLOCAL _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GETLOCAL, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_match + */ +#define CMD_NAMESERVER_MATCH _IOWR(IPC_IOC_MAGIC, NAMESERVER_MATCH, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_remove + */ +#define CMD_NAMESERVER_REMOVE _IOWR(IPC_IOC_MAGIC, NAMESERVER_REMOVE,\ + struct nameserver_cmd_args) + +/* + * Command for nameserver_remove_entry + */ +#define CMD_NAMESERVER_REMOVEENTRY _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_REMOVEENTRY, \ + struct nameserver_cmd_args) + +/* + * Command for nameserver_get_handle + */ +#define CMD_NAMESERVER_GETHANDLE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVER_GETHANDLE, \ + struct nameserver_cmd_args) + +/* + * Command arguments for nameserver + */ + union nameserver_arg { + struct { + struct nameserver_params *params; + } params_init; + + struct { + void *handle; + char *name; + u32 name_len; + struct nameserver_params *params; + } create; + + struct { + void *handle; + } delete_instance; + + struct { + void *handle; + char *name; + u32 name_len; + void *buf; + s32 len; + void *entry; + struct nameserver_entry *node; + } add; + + struct { + void *handle; + char *name; + u32 name_len; + u32 value; + void *entry; + } addu32; + + struct { + void *handle; + char *name; + u32 name_len; + void *buf; + u32 len; + u16 *proc_id; + u32 proc_len; + u32 count; + } get; + + struct { + void *handle; + char *name; + u32 name_len; + void *buf; + u32 len; + u32 count; + } get_local; + + struct { + void *handle; + char *name; + u32 name_len; + u32 *value; + u32 count; + } match; + + struct { + void *handle; + char *name; + u32 name_len; + } remove; + + struct { + void *handle; + void *entry; + } remove_entry; + + struct { + void *handle; + char *name; + u32 name_len; + } get_handle; +}; + +/* + * Command arguments for nameserver + */ +struct nameserver_cmd_args { + union nameserver_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for nameserver module + */ +int nameserver_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _NAMESERVER_IOCTL_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remote.h b/arch/arm/plat-omap/include/syslink/nameserver_remote.h new file mode 100755 index 000000000000..dbdcedfc7ac3 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_remote.h @@ -0,0 +1,39 @@ +/* + * nameserver_remote.h + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTE_H_ +#define _NAMESERVER_REMOTE_H_ + +#include <linux/types.h> + +/* + * Structure defining object for the nameserver remote driver + */ +struct nameserver_remote_object { + int (*get)(const struct nameserver_remote_object *obj, + const char *instance_name, const char *name, + void *value, u32 value_len, void *reserved); + /* Function to get data from remote nameserver */ + void *obj; /* Implementation specific object */ +}; + +/* + * Function get data from remote name server + */ +int nameserver_remote_get(const struct nameserver_remote_object *handle, + const char *instance_name, const char *name, + void *value, u32 value_len); + +#endif /* _NAMESERVER_REMOTE_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h new file mode 100755 index 000000000000..852da8effcc6 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify.h @@ -0,0 +1,100 @@ +/* + * nameserver_remotenotify.h + * + * The nameserver_remotenotify module provides functionality to get name + * value pair from a remote nameserver. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVER_REMOTENOTIFY_H_ +#define _NAMESERVER_REMOTENOTIFY_H_ + +#include <linux/types.h> + +/* + * NAMESERVERREMOTENOTIFY_MODULEID + * Unique module ID + */ +#define NAMESERVERREMOTENOTIFY_MODULEID (0x08FD) + +/* + * Module configuration structure + */ +struct nameserver_remotenotify_config { + u32 reserved; + /* Reserved value (not currently used) */ +}; + +/* + * Module configuration structure + */ +struct nameserver_remotenotify_params { + u32 notify_event_no; /* Notify event number */ + void *notify_driver; /* Notify Driver handle */ + void *shared_addr; /* Address of the shared memory */ + u32 shared_addr_size; /* Size of the shared memory */ + void *gate; /* Handle to the gate used for protecting + nameserver add and delete */ +}; + +/* + * Function to get the default configuration for the nameserver_remotenotify + * module + */ +void nameserver_remotenotify_get_config( + struct nameserver_remotenotify_config *cfg); + +/* + * Function to setup the nameserver_remotenotify module + */ +int nameserver_remotenotify_setup(struct nameserver_remotenotify_config *cfg); + +/* + * Function to destroy the nameserver_remotenotify module + */ +int nameserver_remotenotify_destroy(void); + +/* + * Function to get the current configuration values + */ +void nameserver_remotenotify_params_init(void *handle, + struct nameserver_remotenotify_params *params); + +/* + * Function to setup the Name Server remote notify + */ +void *nameserver_remotenotify_create(u16 proc_id, + const struct nameserver_remotenotify_params *params); + +/* + * Function to destroy the Name Server remote notify + */ +int nameserver_remotenotify_delete(void **handle); + + +/* + * Function to get a name/value from remote nameserver + */ +int nameserver_remotenotify_get(void *handle, + const char *instance_name, const char *name, + void *value, u32 value_len, void *reserved); + +/* + * Get the shared memory requirements for the nameserver_remotenotify + */ +u32 nameserver_remotenotify_shared_memreq( + const struct nameserver_remotenotify_params *params); + + +#endif /* _NAMESERVER_REMOTENOTIFY_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/nameserver_remotenotify_ioctl.h b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify_ioctl.h new file mode 100755 index 000000000000..e8a355456c09 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/nameserver_remotenotify_ioctl.h @@ -0,0 +1,163 @@ +/* + * nameserver_remotenotify_ioctl.h + * + * The nameserver_remotenotify module provides functionality to get name + * value pair from a remote nameserver. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _NAMESERVERREMOTENOTIFY_DRVDEFS_H +#define _NAMESERVERREMOTENOTIFY_DRVDEFS_H + + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <nameserver_remotenotify.h> + +enum CMD_NAMESERVERREMOTENOTIFY { + NAMESERVERREMOTENOTIFY_GETCONFIG = NAMESERVERREMOTENOTIFY_BASE_CMD, + NAMESERVERREMOTENOTIFY_SETUP, + NAMESERVERREMOTENOTIFY_DESTROY, + NAMESERVERREMOTENOTIFY_PARAMS_INIT, + NAMESERVERREMOTENOTIFY_CREATE, + NAMESERVERREMOTENOTIFY_DELETE, + NAMESERVERREMOTENOTIFY_GET, + NAMESERVERREMOTENOTIFY_SHAREDMEMREQ +}; + + +/* + * IOCTL command IDs for nameserver_remotenotify + * + */ + +/* + * Command for nameserver_remotenotify_get_config + */ +#define CMD_NAMESERVERREMOTENOTIFY_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_GETCONFIG, \ + struct nameserver_remotenotify_cmd_args) +/* + * Command for nameserver_remotenotify_setup + */ +#define CMD_NAMESERVERREMOTENOTIFY_SETUP _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_SETUP, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_setup + */ +#define CMD_NAMESERVERREMOTENOTIFY_DESTROY _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_DESTROY, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_destroy + */ +#define CMD_NAMESERVERREMOTENOTIFY_PARAMS_INIT _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_PARAMS_INIT, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_create + */ +#define CMD_NAMESERVERREMOTENOTIFY_CREATE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_CREATE, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_delete + */ +#define CMD_NAMESERVERREMOTENOTIFY_DELETE _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_DELETE, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_get + */ +#define CMD_NAMESERVERREMOTENOTIFY_GET _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_GET, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command for nameserver_remotenotify_shared_memreq + */ +#define CMD_NAMESERVERREMOTENOTIFY_SHAREDMEMREQ _IOWR(IPC_IOC_MAGIC, \ + NAMESERVERREMOTENOTIFY_SHAREDMEMREQ, \ + struct nameserver_remotenotify_cmd_args) + +/* + * Command arguments for nameserver_remotenotify + */ +union nameserver_remotenotify_arg { + struct { + struct nameserver_remotenotify_config *config; + } get_config; + + struct { + struct nameserver_remotenotify_config *config; + } setup; + + struct { + void *handle; + struct nameserver_remotenotify_params *params; + } params_init; + + struct { + void *handle; + u16 proc_id; + struct nameserver_remotenotify_params *params; + } create; + + struct { + void *handle; + } delete_instance; + + struct { + void *handle; + char *instance_name; + u32 instance_name_len; + char *name; + u32 name_len; + u8 *value; + s32 value_len; + void *reserved; + s32 len; + } get; + + struct { + void *handle; + struct nameserver_remotenotify_params *params; + u32 shared_mem_size; + } shared_memreq; +}; + +/* + * Command arguments for nameserver_remotenotify + */ +struct nameserver_remotenotify_cmd_args { + union nameserver_remotenotify_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for nameserver_remotenotify module + */ +int nameserver_remotenotify_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + + +#endif /* _NAMESERVERREMOTENOTIFY_DRVDEFS_H */ + diff --git a/arch/arm/plat-omap/include/syslink/notify.h b/arch/arm/plat-omap/include/syslink/notify.h new file mode 100755 index 000000000000..6cf0e943b85d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify.h @@ -0,0 +1,267 @@ +/* + * notify.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFY_H +#define NOTIFY_H + +#include <syslink/host_os.h> + +#define NOTIFY_MAX_DRIVERS 16 + +/* + * desc Maximum length of the name of Notify drivers, inclusive of NULL + * string terminator. + * + */ +#define NOTIFY_MAX_NAMELEN 32 + +#define NOTIFY_MODULEID 0x5f84 + +/* + *Status code base for Notify module. + */ +#define NOTIFY_STATUSCODEBASE (NOTIFY_MODULEID << 12u) + +/* + * Macro to make error code. + */ +#define NOTIFY_MAKE_FAILURE(x) ((int)(0x80000000\ + | (NOTIFY_STATUSCODEBASE + (x)))) + +/* + * Macro to make success code. + */ +#define NOTIFY_MAKE_SUCCESS(x) (NOTIFY_STATUSCODEBASE + (x)) + +/* + * Generic failure. + */ +#define NOTIFY_E_FAIL NOTIFY_MAKE_FAILURE(1) + +/* + * A timeout occurred while performing the specified operation. + */ +#define NOTIFY_E_TIMEOUT NOTIFY_MAKE_FAILURE(2) + +/* + *Configuration failure. + */ +#define NOTIFY_E_CONFIG NOTIFY_MAKE_FAILURE(3) + +/* + * The module is already initialized + */ +#define NOTIFY_E_ALREADYINIT NOTIFY_MAKE_FAILURE(4) + +/* + * Unable to find the specified entity (e.g. registered event, driver). + */ +#define NOTIFY_E_NOTFOUND NOTIFY_MAKE_FAILURE(5) + +/* + * The specified operation is not supported. + */ +#define NOTIFY_E_NOTSUPPORTED NOTIFY_MAKE_FAILURE(6) + +/* +* Invalid event number specified to the Notify operation. + */ +#define NOTIFY_E_INVALIDEVENT NOTIFY_MAKE_FAILURE(7) + +/* + * Invalid pointer provided. + */ +#define NOTIFY_E_POINTER NOTIFY_MAKE_FAILURE(8) +/* + * The specified value is out of valid range. + */ +#define NOTIFY_E_RANGE NOTIFY_MAKE_FAILURE(9) + +/* An invalid handle was provided. + */ +#define NOTIFY_E_HANDLE NOTIFY_MAKE_FAILURE(10) + +/* + * An invalid argument was provided to the API. + */ +#define NOTIFY_E_INVALIDARG NOTIFY_MAKE_FAILURE(11) + +/* + * A memory allocation failure occurred. + */ +#define NOTIFY_E_MEMORY NOTIFY_MAKE_FAILURE(12) + +/* + * The module has not been setup. + */ +#define NOTIFY_E_INVALIDSTATE NOTIFY_MAKE_FAILURE(13) + +/* + * Maximum number of supported drivers have already been registered. + */ +#define NOTIFY_E_MAXDRIVERS NOTIFY_MAKE_FAILURE(14) + +/* + * Invalid attempt to use a reserved event number. + */ +#define NOTIFY_E_RESERVEDEVENT NOTIFY_MAKE_FAILURE(15) + +/* + * The specified entity (e.g. driver) already exists. + */ +#define NOTIFY_E_ALREADYEXISTS NOTIFY_MAKE_FAILURE(16) + +/* + * brief The Notify driver has not been initialized. + */ +#define NOTIFY_E_DRIVERINIT NOTIFY_MAKE_FAILURE(17) + +/* +* The remote processor is not ready to receive the event. + */ +#define NOTIFY_E_NOTREADY NOTIFY_MAKE_FAILURE(18) + +/* + * brief Failed to register driver with Notify module. + */ +#define NOTIFY_E_REGDRVFAILED NOTIFY_MAKE_FAILURE(19) + +/* +* Failed to unregister driver with Notify module. + */ +#define NOTIFY_E_UNREGDRVFAILED NOTIFY_MAKE_FAILURE(20) + +/* +* Failure in an OS-specific operation. + */ +#define NOTIFY_E_OSFAILURE NOTIFY_MAKE_FAILURE(21) + +/* + *Maximum number of supported events have already been registered. + */ +#define NOTIFY_E_MAXEVENTS NOTIFY_MAKE_FAILURE(22) + +/* Maximum number of supported user clients have already been + * registered. + */ +#define NOTIFY_E_MAXCLIENTS NOTIFY_MAKE_FAILURE(23) + +/* Operation is successful. + */ +#define NOTIFY_SUCCESS NOTIFY_MAKE_SUCCESS(0) + +/* The ProcMgr module has already been setup in this process. + */ +#define NOTIFY_S_ALREADYSETUP NOTIFY_MAKE_SUCCESS(1) + +/* Other ProcMgr clients have still setup the ProcMgr module. + */ +#define NOTIFY_S_SETUP NOTIFY_MAKE_SUCCESS(2) + +/* Other ProcMgr handles are still open in this process. + */ +#define NOTIFY_S_OPENHANDLE NOTIFY_MAKE_SUCCESS(3) + +/* The ProcMgr instance has already been created/opened in this process + */ +#define NOTIFY_S_ALREADYEXISTS NOTIFY_MAKE_SUCCESS(4) + +/* Maximum depth for nesting Notify_disable / Notify_restore calls. + */ +#define NOTIFY_MAXNESTDEPTH 2 + + +/* brief Macro to make a correct module magic number with refCount */ +#define NOTIFY_MAKE_MAGICSTAMP(x) ((NOTIFY_MODULEID << 12u) | (x)) + + +/* + * const NOTIFYSHMDRV_DRIVERNAME + * + * desc Name of the Notify Shared Memory Mailbox driver. + * + */ +#define NOTIFYMBXDRV_DRIVERNAME "NOTIFYMBXDRV" + +#define REG volatile +/* + * const NOTIFYSHMDRV_RESERVED_EVENTS + * + * desc Maximum number of events marked as reserved events by the + * notify_shmdrv driver. + * If required, this value can be changed by the system integrator. + * + */ +#define NOTIFYSHMDRV_RESERVED_EVENTS 3 + +/* +* This key must be provided as the upper 16 bits of the eventNo when + * registering for an event, if any reserved event numbers are to be + * used. + */ +#define NOTIFY_SYSTEM_KEY 0xC1D2 + +struct notify_config { + u32 maxDrivers; + /* Maximum number of drivers that can be created for Notify at a time */ +}; + +typedef void (*notify_callback_fxn)(u16 proc_id, u32 eventNo, void *arg, + u32 payload); + +extern struct notify_module_object notify_state; + +/* Function to get the default configuration for the Notify module. */ +void notify_get_config(struct notify_config *cfg); + +/* Function to setup the Notify Module */ +int notify_setup(struct notify_config *cfg); + +/* Function to destroy the Notify module */ +int notify_destroy(void); + +/* Function to register an event */ +int notify_register_event(void *notify_driver_handle, u16 proc_id, + u32 event_no, + notify_callback_fxn notify_callback_fxn, + void *cbck_arg); + +/* Function to unregister an event */ +int notify_unregister_event(void *notify_driver_handle, u16 proc_id, + u32 event_no, + notify_callback_fxn notify_callback_fxn, + void *cbck_arg); + +/* Function to send an event to other processor */ +int notify_sendevent(void *notify_driver_handle, u16 proc_id, + u32 event_no, u32 payload, bool wait_clear); + +/* Function to disable Notify module */ +u32 notify_disable(u16 procId); + +/* Function to restore Notify module state */ +void notify_restore(u32 key, u16 proc_id); + +/* Function to disable particular event */ +void notify_disable_event(void *notify_driver_handle, u16 proc_id, + u32 event_no); + +/* Function to enable particular event */ +void notify_enable_event(void *notify_driver_handle, u16 proc_id, u32 event_no); + +#endif /* !defined NOTIFY_H */ + diff --git a/arch/arm/plat-omap/include/syslink/notify_dispatcher.h b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h new file mode 100755 index 000000000000..efd87315815e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_dispatcher.h @@ -0,0 +1,158 @@ +/* + * notify_dispatcher.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef __TMBX_H__ +#define __TMBX_H__ + + +#include <syslink/notifydefs.h> +#include <linux/interrupt.h> + +#include <syslink/notifyerr.h> + +#define MAX_MBOX_MODULES 2 +#define MAX_MBOX_ISRS 32 +#define KErrNone 0 +#define KErrNotSupported 1 +#define KErrNotReady 2 +#define KErrArgument 2 + +typedef void (*isr_call_back)(void *); + +struct mbox_config { + unsigned long int mbox_linear_addr; + unsigned long int mbox_modules; + signed long int interrupt_lines[MAX_MBOX_MODULES]; + signed long int mailboxes[MAX_MBOX_MODULES]; +}; + +struct mbox_isrs { + signed long int isrNo[MAX_MBOX_MODULES]; + /* TODO: Remove this - seems to be unused.*/ + isr_call_back isrs[MAX_MBOX_MODULES][MAX_MBOX_ISRS]; + void *isr_params[MAX_MBOX_MODULES][MAX_MBOX_ISRS]; +}; + +extern const unsigned long *linear_address; + +irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p); + +/* + *func ntfy_disp_bind_interrupt + * + * desc Bind an ISR to the HW interrupt line coming into the processor + */ +int ntfy_disp_bind_interrupt(int interrupt_no, + isr_call_back hw_isr, + void *isr_arg); + + +/* + * desc Print the mailbox registers and other useful debug information + * + */ +void ntfy_disp_debug(void); + + +/* + * func ntfy_disp_deinit + * desc Uninitialize the Mailbox Manager module + */ +int ntfy_disp_deinit(void); + + +/* + * desc Return the pointer to the Mailbox Manager's configuration object + */ +struct mbox_config *ntfy_disp_get_config(void); + + +/* + * desc Initialize the Mailbox Manager module + */ +int ntfy_disp_init(void); + + +/* + * desc Disable a particular IRQ bit on a Mailbox IRQ Enable Register + */ +int ntfy_disp_interrupt_disable(unsigned long int mbox_module_no, + int a_irq_bit); + + +/* + * desc Enable a particular IRQ bit on a Mailbox IRQ Enable Register + */ +int ntfy_disp_interrupt_enable(unsigned long int mbox_module_no, + int a_irq_bit); + + +/* + * desc Read a message on a Mailbox FIFO queue + */ +int ntfy_disp_read(unsigned long int mbox_module_no, + int a_mbox_no, + int *messages, + int *num_messages, + short int read_all); + + +/* + * func ntfy_disp_register + * desc Register a ISR callback associated with a particular IRQ bit on a + * Mailbox IRQ Enable Register + */ +int ntfy_disp_register(unsigned long int mbox_module_no, + int a_irq_bit, + isr_call_back isr_cbck_fn, + void *isrCallbackArgs); + + +/* + * func ntfy_disp_send + * desc Send a message on a Mailbox FIFO queue + */ +int ntfy_disp_send(unsigned long int mbox_module_no, + int a_mbox_no, + int message); + + +/* + * func ntfy_disp_unbind_interrupt + * desc Remove the ISR to the HW interrupt line coming into the processor + */ +int ntfy_disp_unbind_interrupt(int interrupt_no); + + +/* + * func ntfy_disp_unregister + * desc Unregister a ISR callback associated with a particular IRQ bit on a + * Mailbox IRQ Enable Register + */ +int ntfy_disp_unregister(unsigned long int mbox_module_no, + int a_irq_bit); + +/* + * func notify_mailbx0_user0_isr + * desc mail ISR + * + */ + +irqreturn_t notify_mailbx0_user0_isr(int temp, void *anArg, struct pt_regs *p); + + +#endif diff --git a/arch/arm/plat-omap/include/syslink/notify_driver.h b/arch/arm/plat-omap/include/syslink/notify_driver.h new file mode 100755 index 000000000000..30a150174654 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_driver.h @@ -0,0 +1,44 @@ +/* + * notify_driver.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFYDRIVER_H +#define NOTIFYDRIVER_H + +#include<linux/list.h> + +/* ----------------------------------- Notify */ +#include <syslink/notifyerr.h> + +/* ----------------------------------- Notify driver */ +#include <syslink/notify_driverdefs.h> + +/* Function to register notify driver */ +int notify_register_driver(char *driver_name, + struct notify_interface *fn_table, + struct notify_driver_attrs *drv_attrs, + struct notify_driver_object **driver_handle); + + +/* Function to unregister notify driver */ +int notify_unregister_driver(struct notify_driver_object *drv_handle); + +/* Function to find the driver in the list of drivers */ +int notify_get_driver_handle(char *driver_name, + struct notify_driver_object **handle); + +#endif /* !defined (NOTIFYDRIVER_H) */ + diff --git a/arch/arm/plat-omap/include/syslink/notify_driverdefs.h b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h new file mode 100755 index 000000000000..0e79562d0867 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_driverdefs.h @@ -0,0 +1,440 @@ +/* + * notify_driverdefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFYDRIVERDEFS_H +#define NOTIFYDRIVERDEFS_H + + +#include <syslink/host_os.h> + +/* ----------------------------------- Notify */ +#include <syslink/notify.h> +#include <syslink/notify_shmdriver.h> +#include <syslink/notifydefs.h> +#include <syslink/multiproc.h> + +#define NOTIFY_BASE_CMD (0x100) + +/* + * Command for Notify_getConfig + */ +#define CMD_NOTIFY_GETCONFIG (NOTIFY_BASE_CMD + 1u) + +/* + * Command for Notify_setup + */ +#define CMD_NOTIFY_SETUP (NOTIFY_BASE_CMD + 2u) + +/* + * Command for Notify_destroy + */ +#define CMD_NOTIFY_DESTROY (NOTIFY_BASE_CMD + 3u) + +/* + * Command for Notify_registerEvent + */ +#define CMD_NOTIFY_REGISTEREVENT (NOTIFY_BASE_CMD + 4u) + +/* + * Command for Notify_unregisterEvent + */ +#define CMD_NOTIFY_UNREGISTEREVENT (NOTIFY_BASE_CMD + 5u) + +/* + * Command for Notify_sendEvent + */ +#define CMD_NOTIFY_SENDEVENT (NOTIFY_BASE_CMD + 6u) + +/* + * Command for Notify_disable + */ +#define CMD_NOTIFY_DISABLE (NOTIFY_BASE_CMD + 7u) + +/* + * Command for Notify_restore + */ +#define CMD_NOTIFY_RESTORE (NOTIFY_BASE_CMD + 8u) + +/* + * Command for Notify_disableEvent + */ +#define CMD_NOTIFY_DISABLEEVENT (NOTIFY_BASE_CMD + 9u) + +/* + * Command for Notify_enableEvent + */ +#define CMD_NOTIFY_ENABLEEVENT (NOTIFY_BASE_CMD + 10u) + +/*! + * @brief Command for Notify_attach + */ +#define CMD_NOTIFY_ATTACH (NOTIFY_BASE_CMD + 11u) + +/*! + * @brief Command for Notify_detach + */ +#define CMD_NOTIFY_DETACH (NOTIFY_BASE_CMD + 12u) + +/* + * const NOTIFY_SYSTEM_KEY_MASK + * + * desc Mask to check for system key. + * + */ + +#define NOTIFY_SYSTEM_KEY_MASK (unsigned short int) 0xFFFF0000 + +/* + * const NOTIFY_EVENT_MASK + * + * desc Mask to check for event ID. + * + */ + +#define NOTIFY_EVENT_MASK (unsigned short int) 0x0000FFFF + +struct notify_cmd_args { + int apiStatus; + /* Status of the API being called. */ +}; + +/* + * Command arguments for Notify_getConfig + */ +struct notify_cmd_args_get_config { + struct notify_cmd_args commonArgs; + struct notify_config *cfg; +}; + +/* + * Command arguments for Notify_setup + */ +struct notify_cmd_args_setup { + struct notify_cmd_args commonArgs; + struct notify_config *cfg; +}; + +/* + * Command arguments for Notify_destroy + */ +struct notify_cmd_args_destroy { + struct notify_cmd_args commonArgs; +}; + +/* + * Command arguments for Notify_registerEvent + */ +struct notify_cmd_args_register_event { + struct notify_cmd_args commonArgs; + struct notify_driver_object *handle; + u16 procId; + u32 eventNo; + notify_callback_fxn fnNotifyCbck; + void *cbckArg; + u32 pid; +}; + +/* + * Command arguments for Notify_unregisterEvent + */ +struct notify_cmd_args_unregister_event { + struct notify_cmd_args commonArgs; + struct notify_driver_object *handle; + u16 procId; + u32 eventNo; + notify_callback_fxn fnNotifyCbck; + void *cbckArg; + u32 pid; +}; + +/* + * Command arguments for Notify_sendEvent + */ +struct notify_cmd_args_send_event { + struct notify_cmd_args commonArgs; + struct notify_driver_object *handle; + u16 procId; + u32 eventNo; + u32 payload; + bool waitClear; +}; + +/* + * Command arguments for Notify_disable + */ +struct notify_cmd_args_disable { + struct notify_cmd_args commonArgs; + u16 procId; + u32 flags; +}; + +/* + * Command arguments for Notify_restore + */ +struct notify_cmd_args_restore { + struct notify_cmd_args commonArgs; + u32 key; + u16 procId; +}; + +/* + * Command arguments for Notify_disableEvent + */ +struct notify_cmd_args_disable_event { + struct notify_cmd_args commonArgs; + struct notify_driver_object *handle; + u16 procId; + u32 eventNo; +}; + +/* + * Command arguments for Notify_enableEvent + */ +struct notify_cmd_args_enable_event { + struct notify_cmd_args commonArgs; + void *notify_driver_handle; + u16 procId; + u32 eventNo; +}; + +/* + * Command arguments for Notify_exit + */ +struct notify_cmd_args_exit { + struct notify_cmd_args commonArgs; +}; + + +enum { + NOTIFY_DRIVERINITSTATUS_NOTDONE = 0, + /* Driver initialization is not done. */ + NOTIFY_DRIVERINITSTATUS_DONE = 1, + /* Driver initialization is complete. */ + NOTIFY_DRIVERINITSTATUS_INPROGRESS = 2, + /* Driver initialization is in progress. */ + NOTIFY_DRIVERINITSTATUS_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + *This structure defines information for all processors supported by + *the Notify driver. + *An instance of this object is provided for each processor handled by + *the Notify driver, when registering itself with the Notify module. + * + */ +struct notify_driver_proc_info { + u32 max_events; + u32 reserved_events; + bool event_priority; + u32 payload_size; + u16 proc_id; +}; + +/* + * This structure defines the structure for specifying Notify driver + * attributes to the Notify module. + * This structure provides information about the Notify driver to the + * Notify module. The information is used by the Notify module mainly + * for parameter validation. It may also be used by the Notify module + * to take appropriate action if required, based on the characteristics + * of the Notify driver. + */ +struct notify_driver_attrs { + u32 numProc; + struct notify_driver_proc_info + proc_info[MULTIPROC_MAXPROCESSORS]; +}; + + +/* ======================================== + * Function pointer types + * ======================================== + */ +/* + * This type defines the function to register a callback for an event + * with the Notify driver. + * This function gets called internally from the Notify_registerEvent + * API. The Notify_registerEvent () function passes on the + * request into the Notify driver identified by the Notify Handle. + * + */ +typedef int(*NotifyDriver_RegisterEvent)(struct notify_driver_object *handle, + u16 procId, u32 eventNo, notify_callback_fxn cbckFxn, + void *cbckArg); +/* + * This type defines the function to unregister a callback for an event + * with the Notify driver. + * This function gets called internally from the Notify_unregisterEvent + * API. The Notify_unregisterEvent () function passes on the + * request into the Notify driver identified by the Notify Handle. + * + */ +typedef int(*NotifyDriver_UnregisterEvent) (struct notify_driver_object *handle, + u16 procId, u32 eventNo, notify_callback_fxn cbckFxn, + void *cbckArg); + +/* + * This type defines the function to send a notification event to the + * registered users for this notification on the specified processor. + * This function gets called internally from the Notify_sendEvent () + * API. The Notify_sendEvent () function passes on the initialization + * request into the Notify driver identified by the Notify Handle. + */ +typedef int(*NotifyDriver_SendEvent) (struct notify_driver_object *handle, + u16 procId, u32 eventNo, u32 payload, bool waitClear); + +/* + * This type defines the function to disable all events for the + * specified processor ID. + * This function gets called internally from the Notify_disable () + * API. The Notify_disable () function passes on the request into the + * Notify driver identified by the Notify Handle. + */ +typedef u32(*NotifyDriver_Disable) (struct notify_driver_object *handle, + u16 procId); + +/* + * This type defines the function to restore all events for the + * specified processor ID. + * This function gets called internally from the Notify_restore () + * API. The Notify_restore () function passes on the request into the + * Notify driver identified by the Notify Handle. + */ +typedef void (*NotifyDriver_Restore) (struct notify_driver_object *handle, + u32 key, u16 procId); + +/* + * This type defines the function to disable specified event for the + * specified processor ID. + * This function gets called internally from the Notify_disableEvent () + * API. The Notify_disableEvent () function passes on the request into + * the Notify driver identified by the Notify Handle. + */ +typedef void (*NotifyDriver_DisableEvent) (struct notify_driver_object *handle, + u16 procId, u32 eventNo); + +/* + * This type defines the function to enable specified event for the + * specified processor ID. + * This function gets called internally from the Notify_enableEvent () + * API. The Notify_enableEvent () function passes on the request into + * the Notify driver identified by the Notify Handle. + * + */ +typedef void (*NotifyDriver_EnableEvent) (struct notify_driver_object *handle, + u16 procId, u32 eventNo); + + +/* + * This structure defines the function table interface for the Notify + * driver. + * This function table interface must be implemented by each Notify + * driver and registered with the Notify module. + * + */ +struct notify_interface { + NotifyDriver_RegisterEvent register_event; + /* interface function registerEvent */ + NotifyDriver_UnregisterEvent unregister_event; + /* interface function unregisterEvent */ + NotifyDriver_SendEvent send_event; + /* interface function sendEvent */ + NotifyDriver_Disable disable; + /* interface function disable */ + NotifyDriver_Restore restore; + /* interface function restore */ + NotifyDriver_DisableEvent disable_event; + /* interface function disableEvent */ + NotifyDriver_EnableEvent enable_event; +}; + + +union notify_drv_procevents{ + struct { + struct notify_shmdrv_attrs attrs; + struct notify_shmdrv_ctrl *ctrl_ptr; + } shm_events; + + struct { + /*Attributes */ + unsigned long int num_events; + unsigned long int send_event_pollcount; + /*Control Paramters */ + unsigned long int send_init_status ; + struct notify_shmdrv_eventreg_mask reg_mask ; + } non_shm_events; +}; + + +/* + * This structure defines the Notify driver object and handle used + * internally to contain all information required for the Notify driver + * This object contains all information for the Notify module to be + * able to identify and interact with the Notify driver. + */ +struct notify_driver_object { + int is_init; + struct notify_interface fn_table; + char name[NOTIFY_MAX_NAMELEN]; + struct notify_driver_attrs attrs; + u32 *disable_flag[NOTIFY_MAXNESTDEPTH]; + void *driver_object; +}; + + +struct notify_drv_eventlist { + unsigned long int event_handler_count; + struct list_head listeners; +}; + + + +struct notify_drv_eventlistner{ + struct list_head element; + fn_notify_cbck fn_notify_cbck; + void *cbck_arg; +}; + + +struct notify_drv_proc_module { + + unsigned long int proc_id; + struct notify_drv_eventlist *event_list; + struct notify_shmdrv_eventreg *reg_chart; + union notify_drv_procevents events_obj; +}; + +/* + * Defines the Notify state object, which contains all the module + * specific information. + */ +struct notify_module_object { + atomic_t ref_count; + struct notify_config cfg; + /* Notify configuration structure */ + struct notify_config def_cfg; + /* Default module configuration */ + struct mutex *gate_handle; + /* Handle of gate to be used for local thread safety */ + struct notify_driver_object drivers[NOTIFY_MAX_DRIVERS]; + /* Array of configured drivers. */ + u32 disable_depth; + /* Current disable depth for Notify module. */ +}; +#endif /* !defined (NOTIFYDRIVERDEFS_H) */ + diff --git a/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h new file mode 100644 index 000000000000..16ad80e425a7 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_ducatidriver.h @@ -0,0 +1,200 @@ +/* + * notify_ducatidriver.h + * + * Syslink driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef NOTIFY_DUCATIDRIVER_H_ +#define NOTIFY_DUCATIDRIVER_H_ + + + +/* Notify*/ +#include <syslink/GlobalTypes.h> +#include <syslink/notifyerr.h> +#include <syslink/notify_driverdefs.h> + +/* + * const NOTIFYDUCATI_DRIVERNAME + * + * desc Name of the ducati driver. + * + */ + +#define IPC_BUF_ALIGN 128 +#define IPC_ALIGN(x, y) (unsigned long int)\ +((unsigned long int)((x + y - 1) / y) * y) + + +#define NOTIFYDUCATI_DRIVERNAME "NOTIFY_DUCATIDRV" + +#define REG volatile + + +extern u32 get_ducati_virt_mem(); +extern void unmap_ducati_virt_mem(u32 shm_virt_addr); + +/* +* func notify_mbxdrv_register_event +* +* desc Register a callback for an event with the Notify driver. +* +* +*/ + +int notify_ducatidrv_register_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no, + fn_notify_cbck fn_notify_cbck, + void *cbck_arg) ; + +/* +* func notify_mbxdrv_unregevent +* +* desc Unregister a callback for an event with the Notify driver. +* +* +*/ + +int notify_ducatidrv_unregister_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no, + fn_notify_cbck fn_notify_cbck, + void *cbck_arg) ; + +/* +* func notify_mbxdrv_sendevent +* +* desc Send a notification event to the registered users for this +* notification on the specified processor. +* +* +*/ + +int notify_ducatidrv_sendevent(struct notify_driver_object *handle, + short int proc_id, + int event_no, + int payload, + short int wait_clear) ; + +/* +* func notify_mbxdrv_disable +* +* desc Disable all events for this Notify driver. +* +* +*/ + +void *notify_ducatidrv_disable(struct notify_driver_object *handle); + +/* +* func notify_mbxdrv_restore +* +* desc Restore the Notify driver to the state before the last disable was +* called. +* +* +*/ + +int notify_ducatidrv_restore(struct notify_driver_object *handle, + void *flags) ; + +/* +* func notify_mbxdrv_disable_event +* +* desc Disable a specific event for this Notify driver. +* +* +*/ + +int notify_ducatidrv_disable_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no) ; + +/* +* func notify_mbxdrv_enable_event +* +* desc Enable a specific event for this Notify driver. +* +* +*/ + +int notify_ducatidrv_enable_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no) ; + + +/* +* func notify_mbxdrv_debug +* +* desc Print debug information for the Notify driver. +* +* +*/ + +int notify_ducatidrv_debug(struct notify_driver_object *handle) ; + +struct notify_ducatidrv_params { + int shared_addr; + int shared_addr_size; + int num_events; + int recv_int_id; + int send_int_id; + int remote_proc_id; + int num_reserved_events; + int send_event_poll_count; +} ; + +/* + * struct notify_ducatidrv_config + * + */ + +struct notify_ducatidrv_config { + u32 reserved; +}; + +/* Function to get the default configuration for the Notify module. */ +void notify_ducatidrv_getconfig(struct notify_ducatidrv_config *cfg); + +/* Function to setup the notify ducati driver with the given configuration*/ +int notify_ducatidrv_setup(struct notify_ducatidrv_config *cfg); + +/* Function to destroy the notify ducati driver*/ +int notify_ducatidrv_destroy(void); + +/* Function to create the ducati driver handle and performs initialization. */ + +struct notify_driver_object *notify_ducatidrv_create(char *driver_name, + const struct notify_ducatidrv_params *params); + +/* Function to delete the ducati driver handle and performs de initialization.*/ +int notify_ducatidrv_delete(struct notify_driver_object **handle_ptr); + +/*Function to open the ducati driver */ +int notify_ducatidrv_open(char *driver_name, + struct notify_driver_object **handle_ptr); + +/*Function to close the ducati driver */ +int notify_ducatidrv_close(struct notify_driver_object **handle_ptr); + +/*Function to initialize the given parameters */ +void notify_ducatidrv_params_init(struct notify_driver_object *handle, + struct notify_ducatidrv_params *params); + +#endif /* !defined NOTIFY_SHMDRIVER_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/notify_ducatidriver_defs.h b/arch/arm/plat-omap/include/syslink/notify_ducatidriver_defs.h new file mode 100755 index 000000000000..6d7b508ae533 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_ducatidriver_defs.h @@ -0,0 +1,152 @@ +/* + * notify_ducati_driverdefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef NOTIFY_DUCATIDRV_DEFS +#define NOTIFY_DUCATIDRV_DEFS + +#include <syslink/notify_ducatidriver.h> + +/* + * brief Base structure for NotifyDriverShm command args. This needs to be + * the first field in all command args structures. + */ +struct notify_ducatidrv_cmdargs { + int api_status; +}; + + +/* + * ioctl command IDs for NotifyDriverShm + * + */ +/* + * brief Base command ID for NotifyDriverShm + */ +#define NOTIFYDRIVERSHM_BASE_CMD 0x100 + +/* + * brief Command for NotifyDriverShm_getConfig + */ +#define CMD_NOTIFYDRIVERSHM_GETCONFIG (NOTIFYDRIVERSHM_BASE_CMD + 1u) + +/* + * brief Command for NotifyDriverShm_setup + */ +#define CMD_NOTIFYDRIVERSHM_SETUP (NOTIFYDRIVERSHM_BASE_CMD + 2u) + +/* + * brief Command for NotifyDriverShm_setup + */ +#define CMD_NOTIFYDRIVERSHM_DESTROY (NOTIFYDRIVERSHM_BASE_CMD + 3u) + +/* + * brief Command for NotifyDriverShm_destroy + */ +#define CMD_NOTIFYDRIVERSHM_PARAMS_INIT (NOTIFYDRIVERSHM_BASE_CMD + 4u) + +/* + * brief Command for NotifyDriverShm_create + */ +#define CMD_NOTIFYDRIVERSHM_CREATE (NOTIFYDRIVERSHM_BASE_CMD + 5u) + +/* + * brief Command for NotifyDriverShm_delete + */ +#define CMD_NOTIFYDRIVERSHM_DELETE (NOTIFYDRIVERSHM_BASE_CMD + 6u) + +/* + * brief Command for NotifyDriverShm_open + */ +#define CMD_NOTIFYDRIVERSHM_OPEN (NOTIFYDRIVERSHM_BASE_CMD + 7u) + +/* + * brief Command for NotifyDriverShm_close + */ +#define CMD_NOTIFYDRIVERSHM_CLOSE (NOTIFYDRIVERSHM_BASE_CMD + 8u) + + +/* + * @brief Command arguments for NotifyDriverShm_getConfig + */ +struct notify_ducatidrv_cmdargs_getconfig { + struct notify_ducatidrv_cmdargs common_args; + struct notify_ducatidrv_config *cfg; +}; + +/* + * brief Command arguments for NotifyDriverShm_setup + */ +struct notify_ducatidrv_cmdargs_setup { + struct notify_ducatidrv_cmdargs common_args; + struct notify_ducatidrv_config *cfg; +}; + +/* + * brief Command arguments for NotifyDriverShm_destroy + */ +struct notify_ducatidrv_cmdargs_destroy { + struct notify_ducatidrv_cmdargs common_args; +} ; + +/* + * brief Command arguments for NotifyDriverShm_Params_init + */ + +struct notify_ducatidrv_cmdargs_paramsinit { + struct notify_ducatidrv_cmdargs common_args; + struct notify_driver_object *handle; + struct notify_ducatidrv_params *params; +}; + +/*! + * @brief Command arguments for NotifyDriverShm_create + */ +struct notify_ducatidrv_cmdargs_create { + struct notify_ducatidrv_cmdargs common_args; + char driverName[NOTIFY_MAX_NAMELEN]; + struct notify_ducatidrv_params params; + struct notify_driver_object *handle; +}; + +/* + * brief Command arguments for NotifyDriverShm_delete + */ +struct notify_ducatidrv_cmdargs_delete { + struct notify_ducatidrv_cmdargs common_args; + struct notify_driver_object *handle; +}; + +/* + * brief Command arguments for NotifyDriverShm_open + */ +struct notify_ducatidrv_cmdargs_open { + struct notify_ducatidrv_cmdargs common_args; + char driverName[NOTIFY_MAX_NAMELEN]; + struct notify_driver_object *handle; + +}; + +/* + * brief Command arguments for NotifyDriverShm_close + */ +struct notify_ducatidrv_cmdargs_close { + struct notify_ducatidrv_cmdargs common_args; + struct notify_driver_object *handle; + +}; + +#endif /*NOTIFY_DUCATIDRV_DEFS*/ diff --git a/arch/arm/plat-omap/include/syslink/notify_shmdriver.h b/arch/arm/plat-omap/include/syslink/notify_shmdriver.h new file mode 100755 index 000000000000..450896160bdf --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_shmdriver.h @@ -0,0 +1,108 @@ + +/* + * notify_shmdriver.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFY_SHMDRIVER_H_ +#define NOTIFY_SHMDRIVER_H_ + +/* + * const NOTIFYSHMDRV_DRIVERNAME + * + * desc Name of the Notify Shared Memory Mailbox driver. + * + */ +#define NOTIFYSHMDRV_DRIVERNAME "NOTIFYSHMDRV" + +/* + * const NOTIFYSHMDRV_RESERVED_EVENTS + * + * desc Maximum number of events marked as reserved events by the + * NotiyShmDrv driver. + * If required, this value can be changed by the system integrator. + * + */ + +#define NOTIFYSHMDRV_RESERVED_EVENTS 3 + + +/* + * name notify_shmdrv_attrs + * + */ +struct notify_shmdrv_attrs { + unsigned long int shm_base_addr; + unsigned long int shm_size; + unsigned long int num_events; + unsigned long int send_event_pollcount; +}; + + +/* +* name notify_shmdrv_event_entry +*/ +struct notify_shmdrv_event_entry { + REG unsigned long int flag; + REG unsigned long int payload; + REG unsigned long int reserved; + unsigned long int padding[29]; +}; + +/* +* name notify_shmdrv_eventreg_mask +* +*/ +struct notify_shmdrv_eventreg_mask { + REG unsigned long int mask; + REG unsigned long int enable_mask; + unsigned long int padding[30]; +}; + +/* +* name notify_shmdrv_eventreg +* +*/ +struct notify_shmdrv_eventreg { + unsigned long int reg_event_no; + unsigned long int reserved; +}; + +/* +* name notify_shmdrv_proc_ctrl +* +*/ +struct notify_shmdrv_proc_ctrl { + struct notify_shmdrv_event_entry *self_event_chart; + struct notify_shmdrv_event_entry *other_event_chart; + unsigned long int recv_init_status; + unsigned long int send_init_status; + unsigned long int padding[28]; + struct notify_shmdrv_eventreg_mask reg_mask; + struct notify_shmdrv_eventreg *reg_chart; +}; + +/* + * brief Defines the notify_shmdrv_ctrl structure, which contains all + * information shared between the two connected processors + * This structure is shared between the two processors. + */ +struct notify_shmdrv_ctrl { + struct notify_shmdrv_proc_ctrl proc_ctrl[2]; +}; + +#endif /* !defined NOTIFY_SHMDRIVER_H_ */ + + diff --git a/arch/arm/plat-omap/include/syslink/notify_tesladriver.h b/arch/arm/plat-omap/include/syslink/notify_tesladriver.h new file mode 100755 index 000000000000..50f4ece661f9 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notify_tesladriver.h @@ -0,0 +1,219 @@ +/* + * notify_tesladriver.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + + + +/* Notify*/ +#include <syslink/GlobalTypes.h> +#include <syslink/notifyerr.h> +#include <syslink/notify_driverdefs.h> +#include <syslink/notifydefs.h> + +/* + * const NOTIFYSHMDRV_DRIVERNAME + * + * desc Name of the Notify Shared Memory Mailbox driver. + * + */ +#define NOTIFYMBXDRV_DRIVERNAME "NOTIFYMBXDRV" + +/* +* struct notify_tesladrv_params +* +* desc driver.params +* +*/ + + +struct notify_tesladrv_params { + int shared_addr; + int shared_addr_size; + int num_events; + int recv_int_id; + int send_int_id; + int remote_proc_id; + int num_reserved_events; + int send_event_poll_count; +}; + +/* +* struct notify_tesladrv_config +* +* desc driver.configuration +* +*/ + + +struct notify_tesladrv_config { + u32 reserved; +}; + + + +/* +* func notify_mbxdrv_register_event +* +* desc Register a callback for an event with the Notify driver. +* +* +*/ + +int notify_tesladrv_register_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no, + fn_notify_cbck fn_notify_cbck, + void *cbck_arg); + +/* +* func notify_mbxdrv_unregevent +* +* desc Unregister a callback for an event with the Notify driver. +* +* +*/ + +int notify_tesladrv_unregister_event( + struct notify_driver_object *handle, + short int proc_id, + int event_no, + fn_notify_cbck fn_notify_cbck, + void *cbck_arg); + +/* +* func notify_mbxdrv_sendevent +* +* desc Send a notification event to the registered users for this +* notification on the specified processor. +* +* +*/ + +int notify_tesladrv_sendevent(struct notify_driver_object *handle, + short int proc_id, int event_no, + int payload, short int wait_clear); + +/* +* func notify_mbxdrv_disable +* +* desc Disable all events for this Notify driver. +* +* +*/ + +void *notify_tesladrv_disable(struct notify_driver_object *handle, u16 proc_Id); + +/* +* func notify_mbxdrv_restore +* +* desc Restore the Notify driver to the state before the last disable was +* called. +* +* +*/ + +int notify_tesladrv_restore(struct notify_driver_object *handle, + u32 key, u16 proc_id); + +/* +* func notify_mbxdrv_disable_event +* +* desc Disable a specific event for this Notify driver. +* +* +*/ + +int notify_tesladrv_disable_event(struct notify_driver_object *handle, + short int proc_id, int event_no); + +/* +* func notify_mbxdrv_enable_event +* +* desc Enable a specific event for this Notify driver. +* +* +*/ + +int notify_tesladrv_enable_event(struct notify_driver_object *handle, + short int proc_id, int event_no); + +/* +* func notify_tesladrv_debug +* +* desc Print debug information for the Notify driver. +* +* +*/ + +int notify_tesladrv_debug(struct notify_driver_object *handle); + +/* +* func notify_tesladrv_create +* +* desc creates driver handle. +* +* +*/ + +struct notify_driver_object *notify_tesladrv_create(char *driver_name, + const struct notify_tesladrv_params *params); + +/* +* func notify_tesladrv_delete +* +* desc deletes driver handle. +*/ + + +int notify_tesladrv_delete(struct notify_driver_object **handlePtr); + +/* +* func notify_tesladrv_getconfig +* +* desc Get the default configuration for driver. +*/ +void notify_tesladrv_getconfig(struct notify_tesladrv_config *cfg); + + +/* +* func notify_tesladrv_setup +* +* desc setup the driver with the given config. +*/ + + +int notify_tesladrv_setup(struct notify_tesladrv_config *cfg); + +/* +* func notify_tesladrv_params_init +* +* desc initializes parameters for driver. +*/ + +void notify_tesladrv_params_init(struct notify_driver_object *handle, + struct notify_tesladrv_params *params); + +/* +* func notify_tesladrv_destroy +* +* desc destroys the driver +*/ + +int notify_tesladrv_destroy(void); + + + diff --git a/arch/arm/plat-omap/include/syslink/notifydefs.h b/arch/arm/plat-omap/include/syslink/notifydefs.h new file mode 100755 index 000000000000..7f37346a7f75 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notifydefs.h @@ -0,0 +1,25 @@ +/* + * notifydefs.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFYDEFS_H +#define NOTIFYDEFS_H +typedef void (*fn_notify_cbck) (unsigned long int procId, + u32 eventNo, + void *arg, + u32 payload) ; + +#endif /* !defined (NOTIFYDEFS_H) */ diff --git a/arch/arm/plat-omap/include/syslink/notifyerr.h b/arch/arm/plat-omap/include/syslink/notifyerr.h new file mode 100755 index 000000000000..9bbaa238fa3a --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/notifyerr.h @@ -0,0 +1,198 @@ +/* + * notifyerr.h + * + * Notify driver support for OMAP Processors. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#if !defined NOTIFYERR_H +#define NOTIFYERR_H + + +/* + * name NOTIFY_SUCCEEDED + * + * desc Check if the provided status code indicates a success code. + * + * arg status + * Status code to be checked + * + * ret TRUE + * If status code indicates success + * FALSE + * If status code indicates failure + * + * enter None. + * + * leave None. + * + * see NOTIFY_FAILED + * + */ +#define NOTIFY_SUCCEEDED(status)\ +(((signed long int) (status) >= (NOTIFY_SBASE)) \ +&& ((signed long int) (status) <= (NOTIFY_SLAST))) + + +/* + * @name NOTIFY_FAILED + * + * @desc Check if the provided status code indicates a failure code. + * + * @arg status + * Status code to be checked + * + * @ret TRUE + * If status code indicates failure + * FALSE + * If status code indicates success + * + * @enter None. + * + * @leave None. + * + * @see NOTIFY_FAILED + * + */ +#define NOTIFY_FAILED(status) (!NOTIFY_SUCCEEDED(status)) + + + +/* + * name NOTIFY_SBASE, NOTIFY_SLAST + * + * desc Defines the base and range for the success codes used by the + * Notify module + * + */ +#define NOTIFY_SBASE (signed long int)0x00002000l +#define NOTIFY_SLAST (signed long int)0x000020FFl + +/* + * name NOTIFY_EBASE, NOTIFY_ELAST + * + * desc Defines the base and range for the failure codes used by the + * Notify module + * + */ +#define NOTIFY_EBASE (signed long int)0x80002000l +#define NOTIFY_ELAST (signed long int)0x800020FFl + + +/* + * SUCCESS Codes + * + */ + +/* Generic success code for Notify module */ +#define NOTIFY_SOK (NOTIFY_SBASE + 0x01l) + +/* Indicates that the Notify module (or driver) has already been initialized + * by another client, and this process has now successfully acquired the right + * to use the Notify module. + */ +#define NOTIFY_SALREADYINIT (NOTIFY_SBASE + 0x02l) + +/* Indicates that the Notify module (or driver) is now being finalized, since + * the calling client is the last one finalizing the module, and all open + * handles to it have been closed. + */ +#define NOTIFY_SEXIT (NOTIFY_SBASE + 0x03l) + + +/* + * FAILURE Codes + * + */ + +/* Generic failure code for Notify module */ +#define NOTIFY_EFAIL (NOTIFY_EBASE + 0x01l) + +/* This failure code indicates that an operation has timed out. */ +#define NOTIFY_ETIMEOUT (NOTIFY_EBASE + 0x02l) + +/* This failure code indicates a configuration error */ +#define NOTIFY_ECONFIG (NOTIFY_EBASE + 0x03l) + +/* This failure code indicates that the Notify module has already been + * initialized from the calling client (process). + */ +#define NOTIFY_EALREADYINIT (NOTIFY_EBASE + 0x04l) + +/* This failure code indicates that the specified entity was not found + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ENOTFOUND (NOTIFY_EBASE + 0x05l) + +/* This failure code indicates that the specified feature is not supported + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ENOTSUPPORTED (NOTIFY_EBASE + 0x06l) + +/* This failure code indicates that the specified event number is + * not supported + */ +#define NOTIFY_EINVALIDEVENT (NOTIFY_EBASE + 0x07l) + +/* This failure code indicates that the specified pointer is invalid */ +#define NOTIFY_EPOINTER (NOTIFY_EBASE + 0x08l) + +/* This failure code indicates that a provided parameter was outside its valid + * range. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ERANGE (NOTIFY_EBASE + 0x09l) + +/* This failure code indicates that the specified handle is invalid */ +#define NOTIFY_EHANDLE (NOTIFY_EBASE + 0x0Al) + +/* This failure code indicates that an invalid argument was specified */ +#define NOTIFY_EINVALIDARG (NOTIFY_EBASE + 0x0Bl) + +/* This failure code indicates a memory related failure */ +#define NOTIFY_EMEMORY (NOTIFY_EBASE + 0x0Cl) + +/* This failure code indicates that the Notify module has not been initialized*/ +#define NOTIFY_EINIT (NOTIFY_EBASE + 0x0Dl) + +/* This failure code indicates that a resource was not available. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_ERESOURCE (NOTIFY_EBASE + 0x0El) + +/* This failure code indicates that there was an attempt to register for a + * reserved event. + */ +#define NOTIFY_ERESERVEDEVENT (NOTIFY_EBASE + 0x0Fl) + +/* This failure code indicates that the specified entity already exists. + * The interpretation of this error code depends on the function from which it + * was returned. + */ +#define NOTIFY_EALREADYEXISTS (NOTIFY_EBASE + 0x10l) + +/* This failure code indicates that the Notify driver has not been fully + * initialized + */ +#define NOTIFY_EDRIVERINIT (NOTIFY_EBASE + 0x11l) + +/* This failure code indicates that the other side is not ready to receive + * notifications. + */ +#define NOTIFY_ENOTREADY (NOTIFY_EBASE + 0x12l) + +#endif /* !defined (NOTIFYERR_H) */ diff --git a/arch/arm/plat-omap/include/syslink/platform.h b/arch/arm/plat-omap/include/syslink/platform.h new file mode 100644 index 000000000000..298d20f7ab5d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/platform.h @@ -0,0 +1,45 @@ +/* + * platform.h + * + * Defines the platform functions to be used by SysMgr module. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +/* Module headers */ +#include <sysmgr.h> + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Function to setup the platform */ +s32 platform_setup(struct sysmgr_config *config); + +/* Function to destroy the platform */ +s32 platform_destroy(void); + +/* Function called when slave is loaded with executable */ +void platform_load_callback(void *arg); + +/* Function called when slave is in started state*/ +void platform_start_callback(void *arg); + +/* Function called when slave is stopped state */ +void platform_stop_callback(void *arg); + +s32 platform_override_config(struct sysmgr_config *config); + +#endif /* ifndef _PLATFORM_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/platform_mem.h b/arch/arm/plat-omap/include/syslink/platform_mem.h new file mode 100755 index 000000000000..874a1153fc21 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/platform_mem.h @@ -0,0 +1,137 @@ +/* + * platform_mem.c + * + * Target memory management interface implementation. + * + * This abstracts the Memory management interface in the kernel + * code. Allocation, Freeing-up, copy and address translate are + * supported for the kernel memory management. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _PLATFORM_MEM_H_ +#define _PLATFORM_MEM_H_ + +#include <linux/types.h> + +/* + * MEMORYOS_MODULEID + * Module ID for platform mem module + */ +#define PLATFORM_MEM_MODULEID (u16) 0x97D2 + +/* + * Enumerates the types of caching for memory regions + */ +enum platform_mem_cache_flags { + PLATFORM_MEM_CACHE_FLAGS_DEFAULT = 0x00000000, + /* Default flags - Cached */ + PLATFORM_MEM_CACHE_FLAGS_CACHED = 0x00010000, + /* Cached memory */ + PLATFORM_MEM_CACHE_FLAGS_UNCACHED = 0x00020000, + /* Uncached memory */ + PLATFORM_MEM_CACHE_FLAGS_END_VALUE = 0x00030000 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerates the types of memory allocation + */ +enum platform_mem_mtype_flags{ + PLATFORM_MEM_MTYPE_FLAGS_DEFAULT = 0x00000000, + /* Default flags - virtually contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_PHYSICAL = 0x00000001, + /* Physically contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_DMA = 0x00000002, + /* Physically contiguous */ + PLATFORM_MEM_MTYPE_FLAGS_END_VALUE = 0x00000003 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerates the types of translation + */ +enum memory_xlt_flags{ + PLATFORM_MEM_XLT_FLAGS_VIRT2PHYS = 0x00000000, + /* Virtual to physical */ + PLATFORM_MEM_XLT_FLAGS_PHYS2VIRT = 0x00000001, + /* Virtual to physical */ + PLATFORM_MEM_XLT_FLAGS_END_VALUE = 0x00000002 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Structure containing information required for mapping a + * memory region. + */ +struct platform_mem_map_info { + u32 src; + /* Address to be mapped. */ + u32 size; + /* Size of memory region to be mapped. */ + u32 dst; + /* Mapped address. */ + bool is_cached; + /* Whether the mapping is to a cached area or uncached area. */ + void *drv_handle; + /* Handle to the driver that is implementing the mmap call. Ignored for + Kernel-side version. */ +}; + +/* + * Structure containing information required for unmapping a + * memory region. + */ +struct platform_mem_unmap_info { + u32 addr; + /* Address to be unmapped.*/ + u32 size; + /* Size of memory region to be unmapped.*/ + bool is_cached; + /* Whether the mapping is to a cached area or uncached area. */ +}; + +/* + * Structure containing information required for mapping a + * memory region. + */ +#define memory_map_info struct platform_mem_map_info + +/* + * Structure containing information required for unmapping a + * memory region. + */ +#define memory_unmap_info struct platform_mem_unmap_info + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Initialize the platform mem module. */ +int platform_mem_setup(void); + +/* Finalize the platform mem module. */ +int platform_mem_destroy(void); + +/* Maps a memory area into virtual space. */ +int platform_mem_map(memory_map_info *map_info); + +/* Unmaps a memory area into virtual space. */ +int platform_mem_unmap(memory_unmap_info *unmap_info); + +/* Translate API */ +void *platform_mem_translate(void *srcAddr, enum memory_xlt_flags flags); + +#endif /* ifndef _PLATFORM_MEM_H_ */ + diff --git a/arch/arm/plat-omap/include/syslink/procmgr.h b/arch/arm/plat-omap/include/syslink/procmgr.h new file mode 100755 index 000000000000..4d113c9fa90d --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/procmgr.h @@ -0,0 +1,280 @@ +/* + * procmgr.h + * + * Syslink driver support functions for TI OMAP processors. + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef SYSLINK_PROC_MGR_H +#define SYSLINK_PROC_MGR_H + +#include <linux/types.h> +#include <syslink/multiproc.h> + + + +#define PROCMGR_MODULEID 0xf2ba + +/* + * Maximum name length for ProcMgr module strings. + */ +#define PROCMGR_MAX_STRLEN 32 + +/* + * Maximum number of memory regions supported by ProcMgr module. + */ +#define PROCMGR_MAX_MEMORY_REGIONS 32 + +/* + * IS_VALID_PROCID + * Checks if the Processor ID is valid + */ +#define IS_VALID_PROCID(id) (id < MULTIPROC_MAXPROCESSORS) + + +/* + * Enumerations to indicate Processor states. + */ +enum proc_mgr_state { + PROC_MGR_STATE_UNKNOWN = 0, + /* Unknown Processor state (e.g. at startup or error). */ + PROC_MGR_STATE_POWERED = 1, + /* Indicates the Processor is powered up. */ + PROC_MGR_STATE_RESET = 2, + /* Indicates the Processor is reset. */ + PROC_MGR_STATE_LOADED = 3, + /* Indicates the Processor is loaded. */ + PROC_MGR_STATE_RUNNNING = 4, + /* Indicates the Processor is running. */ + PROC_MGR_STATE_UNAVAILABLE = 5, + /* Indicates the Processor is unavailable to the physical transport. */ + PROC_MGR_STATE_ENDVALUE = 6 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerations to indicate different types of slave boot modes. + */ +enum proc_mgr_boot_mode { + PROC_MGR_BOOTMODE_BOOT = 0, + /* ProcMgr is responsible for loading the slave and its reset control */ + PROC_MGR_BOOTMODE_NOLOAD = 1, + /* ProcMgr is not responsible for loading the slave. It is responsible + for reset control of the slave. */ + PROC_MGR_BOOTMODE_NOBOOT = 2, + /* ProcMgr is not responsible for loading or reset control of the slave. + The slave either self-boots, or this is done by some entity outside of + the ProcMgr module. */ + PROC_MGR_BOOTMODE_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +} ; + +/* + * Enumerations to indicate address types used for translation + */ +enum proc_mgr_addr_type{ + PROC_MGR_ADDRTYPE_MASTERKNLVIRT = 0, + /* Kernel Virtual address on master processor */ + PROC_MGR_ADDRTYPE_MASTERUSRVIRT = 1, + /* User Virtual address on master processor */ + PROC_MGR_ADDRTYPE_SLAVEVIRT = 2, + /* Virtual address on slave processor */ + PROC_MGR_ADDRTYPE_ENDVALUE = 3 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Enumerations to indicate types of address mapping + */ +enum proc_mgr_map_type { + PROC_MGR_MAPTYPE_VIRT = 0, + /* Map/unmap to virtual address space (kernel/user) */ + PROC_MGR_MAPTYPE_SLAVE = 1, + /* Map/unmap to slave address space */ + PROC_MGR_MAPTYPE_ENDVALUE = 2 + /* End delimiter indicating start of invalid values for this enum */ +}; + +/* + * Module configuration structure. + */ +struct proc_mgr_config { + void *gate_handle; +} ; + +/* + * Configuration parameters specific to the slave ProcMgr instance. + */ +struct proc_mgr_params { + void *proc_handle; + /* void * to the Processor object associated with this ProcMgr. */ + void *loader_handle; + /*!< Handle to the Loader object associated with this ProcMgr. */ + void *pwr_handle; + /*!< Handle to the PwrMgr object associated with this ProcMgr. */ +}; + +/* + * Configuration parameters specific to the slave ProcMgr instance. + */ +struct proc_mgr_attach_params { + enum proc_mgr_boot_mode boot_mode; + /* Boot mode for the slave processor. */ +} ; + +/* + * Configuration parameters to be provided while starting the slave + * processor. + */ +struct proc_mgr_start_params { + u32 proc_id; +}; + +/* + * Configuration parameters to be provided while stopping the slave + * processor. + */ +struct proc_mgr_stop_params { + u32 proc_id; +}; + +/* + * This structure defines information about memory regions mapped by + * the ProcMgr module. + */ +struct proc_mgr_addr_info { +/* bool is_init; */ + unsigned short is_init; + /* Is this memory region initialized? */ + u32 addr[PROC_MGR_ADDRTYPE_ENDVALUE]; + /* Addresses for each type of address space */ + u32 size; + /* Size of the memory region in bytes */ +}; + +/* + * Characteristics of the slave processor + */ +struct proc_mgr_proc_info { + enum proc_mgr_boot_mode boot_mode; + /* Boot mode of the processor. */ + u16 num_mem_entries; + /* Number of valid memory entries */ + struct proc_mgr_addr_info mem_entries[PROCMGR_MAX_MEMORY_REGIONS]; + /* Configuration of memory regions */ +}; + + +/* + * Function pointer type that is passed to the proc_mgr_registerNotify function +*/ +typedef int (*proc_mgr_callback_fxn)(u16 proc_id, void *handle, + enum proc_mgr_state from_state, enum proc_mgr_state to_state); + +/* Function to get the default configuration for the ProcMgr module. */ +void proc_mgr_get_config(struct proc_mgr_config *cfg); + +/* Function to setup the ProcMgr module. */ +int proc_mgr_setup(struct proc_mgr_config *cfg); + +/* Function to destroy the ProcMgr module. */ +int proc_mgr_destroy(void); + +/* Function to initialize the parameters for the ProcMgr instance. */ +void proc_mgr_params_init(void *handle, struct proc_mgr_params *params); + +/* Function to create a ProcMgr object for a specific slave processor. */ +void *proc_mgr_create(u16 proc_id, const struct proc_mgr_params *params); + +/* Function to delete a ProcMgr object for a specific slave processor. */ +int proc_mgr_delete(void **handle_ptr); + +/* Function to open a handle to an existing ProcMgr object handling the + * proc_id. + */ +int proc_mgr_open(void **handle, u16 proc_id); + +/* Function to close this handle to the ProcMgr instance. */ +int proc_mgr_close(void *handle); + +/* Function to initialize the parameters for the ProcMgr attach function. */ +void proc_mgr_get_attach_params(void *handle, + struct proc_mgr_attach_params *params); + +/* Function to attach the client to the specified slave and also initialize the + * slave(if required). + */ +int proc_mgr_attach(void *handle, struct proc_mgr_attach_params *params); + +/* Function to detach the client from the specified slave and also finalze the + * slave(if required). + */ +int proc_mgr_detach(void *handle); + +/* Function to initialize the parameters for the ProcMgr start function. */ +void proc_mgr_get_start_params(void *handle, + struct proc_mgr_start_params *params); + +/* Function to starts execution of the loaded code on the slave from the + * starting point specified in the slave executable loaded earlier by call to + * proc_mgr_load(). + */ +int proc_mgr_start(void *handle, u32 entry_point, + struct proc_mgr_start_params *params); + +/* Function to stop execution of the slave Processor. */ +int proc_mgr_stop(void *handle, struct proc_mgr_stop_params *params); + +/* Function to get the current state of the slave Processor as maintained on + * the master Processor state machine. + */ +enum proc_mgr_state proc_mgr_get_state(void *handle); + +/* Function to read from the slave Processor's memory space. */ +int proc_mgr_read(void *handle, u32 proc_addr, u32 *num_bytes, + void *buffer); + +/* Function to read from the slave Processor's memory space. */ +int proc_mgr_write(void *handle, u32 proc_addr, u32 *num_bytes, void *buffer); + +/* Function that provides a hook for performing device dependent operations on + * the slave Processor. + */ +int proc_mgr_control(void *handle, int cmd, void *arg); + +int proc_mgr_translate_addr(void *handle, void **dst_addr, + enum proc_mgr_addr_type dst_addr_type, void *src_addr, + enum proc_mgr_addr_type src_addr_type); + +/* Function that maps the specified slave address to master address space. */ +int proc_mgr_map(void *handle, u32 proc_addr, u32 size, + u32 *mappedAddr, u32 *mapped_size, u32 map_attribs); + +/* Function that unmaps the specified slave address to master address space. */ +int proc_mgr_unmap(void *handle, u32 mapped_addr); + +/* Function that registers for notification when the slave processor + * transitions to any of the states specified. + */ +int proc_mgr_register_notify(void *handle, proc_mgr_callback_fxn fxn, + void *args, enum proc_mgr_state state[]); + +/* Function that returns information about the characteristics of the slave + * processor. + */ +int proc_mgr_get_proc_info(void *handle, struct proc_mgr_proc_info *proc_info); + +/* Function that returns virtual to physical translations + */ +int proc_mgr_virt_to_phys(void *handle, u32 da, u32 *mapped_entries, + u32 num_of_entries); + +#endif diff --git a/arch/arm/plat-omap/include/syslink/sharedregion.h b/arch/arm/plat-omap/include/syslink/sharedregion.h new file mode 100755 index 000000000000..75fe48049b5e --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sharedregion.h @@ -0,0 +1,110 @@ +/* + * sharedregion.h + * + * The SharedRegion module is designed to be used in a + * multi-processor environment where there are memory regions + * that are shared and accessed across different processors + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SHAREDREGION_H_ +#define _SHAREDREGION_H_ + +#include <linux/types.h> + +/* + * SHAREDREGION_MODULEID + * Module ID for Shared region manager + */ +#define SHAREDREGION_MODULEID (0x5D8A) + +/* + * Name of the reserved nameserver used for application + */ +#define SHAREDREGION_NAMESERVER "SHAREDREGION" + +/* + * Name of the reserved nameserver used for application + */ +#define SHAREDREGION_INVALIDSRPTR ((u32 *)0xFFFFFFFF) + + +struct sharedregion_info { + bool is_valid; /* table entry is valid or not? */ + void *base; /* Ptr to the base address of a table entry */ + u32 len; /* The length of a table entry */ +}; + +/* + * Module configuration structure + */ +struct sharedregion_config { + void *gate_handle; + void *heap_handle; + u32 max_regions; +}; + +/* + * Function to get the configuration + */ +int sharedregion_get_config(struct sharedregion_config *config); + +/* + * Function to setup the SharedRegion module + */ +int sharedregion_setup(const struct sharedregion_config *config); + +/* + * Function to destroy the SharedRegion module + */ +int sharedregion_destroy(void); + +/* Fucntion to Add a memory segment to the lookup table during + * runtime by base and length + */ +int sharedregion_add(u32 index, void *base, u32 len); + +/* Removes the memory segment at the specified index from the lookup + * table at runtime + */ +int sharedregion_remove(u32 index); + +/* + * Returns the index for the specified address pointer + */ +int sharedregion_get_index(void *addr); + +/* + * Returns the address pointer associated with the shared region pointer + */ +void *sharedregion_get_ptr(u32 *srptr); + +/* + * Returns the shared region pointer + */ +u32 *sharedregion_get_srptr(void *addr, int index); + +/* + * Gets the table entry information for the specified index and processor id + */ +int sharedregion_get_table_info(u32 index, u16 proc_id, + struct sharedregion_info *info); + +/* + * Sets the base address of the entry in the table + */ +int sharedregion_set_table_info(u32 index, u16 proc_id, + struct sharedregion_info *info); + +#endif /* _SHAREDREGION_H */ + diff --git a/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h new file mode 100755 index 000000000000..0b2857110991 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sharedregion_ioctl.h @@ -0,0 +1,181 @@ +/* + * sharedregion_ioctl.h + * + * The sharedregion module is designed to be used in a + * multi-processor environment where there are memory regions + * that are shared and accessed across different processors + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SHAREDREGION_IOCTL_H +#define _SHAREDREGION_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#include <ipc_ioctl.h> +#include <sharedregion.h> + +enum CMD_SHAREDREGION { + SHAREDREGION_GETCONFIG = SHAREDREGION_BASE_CMD, + SHAREDREGION_SETUP, + SHAREDREGION_DESTROY, + SHAREDREGION_ADD, + SHAREDREGION_GETPTR, + SHAREDREGION_GETSRPTR, + SHAREDREGION_GETTABLEINFO, + SHAREDREGION_REMOVE, + SHAREDREGION_SETTABLEINFO, + SHAREDREGION_GETINDEX, +}; + +/* + * IOCTL command IDs for sharedregion + * + */ + +/* + * Command for sharedregion_get_config + */ +#define CMD_SHAREDREGION_GETCONFIG _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETCONFIG, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_setup + */ +#define CMD_SHAREDREGION_SETUP _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_SETUP, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_setup + */ +#define CMD_SHAREDREGION_DESTROY _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_DESTROY, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_ADD + */ +#define CMD_SHAREDREGION_ADD _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_ADD, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_get_ptr + */ +#define CMD_SHAREDREGION_GETPTR _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETPTR, \ + struct sharedregion_cmd_args) + +/* + * Command for sharedregion_get_srptr + */ +#define CMD_SHAREDREGION_GETSRPTR _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETSRPTR, \ + struct sharedregion_cmd_args) + +/* + * Command for sharedregion_get_table_info + */ +#define CMD_SHAREDREGION_GETTABLEINFO _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETTABLEINFO, \ + struct sharedregion_cmd_args) + +/* + * Command for sharedregion_remove + */ +#define CMD_SHAREDREGION_REMOVE _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_REMOVE, \ + struct sharedregion_cmd_args) +/* + * Command for sharedregion_set_table_info + */ +#define CMD_SHAREDREGION_SETTABLEINFO _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_SETTABLEINFO, \ + struct sharedregion_cmd_args) + +/* + * Command for sharedregion_get_index + */ +#define CMD_SHAREDREGION_GETINDEX _IOWR(IPC_IOC_MAGIC, \ + SHAREDREGION_GETINDEX, \ + struct sharedregion_cmd_args) + +/* + * Command arguments for sharedregion + */ +union sharedregion_arg { + struct { + struct sharedregion_config *config; + } get_config; + + struct { + struct sharedregion_config *config; + struct sharedregion_config *default_cfg; + struct sharedregion_info *table; + } setup; + + struct { + u32 index; + void *base; + u32 len; + } add; + + struct { + void *addr; + s32 index; + } get_index; + + struct { + u32 *srptr; + void *addr; + } get_ptr; + + struct { + u32 *srptr; + void *addr; + s32 index; + } get_srptr; + + struct { + u32 index; + u16 proc_id; + struct sharedregion_info *info; + } get_table_info; + + struct { + u32 index; + } remove; + + struct { + u32 index; + u16 proc_id; + struct sharedregion_info *info; + } set_table_info; +} ; + +/* + * Command arguments for sharedregion + */ +struct sharedregion_cmd_args { + union sharedregion_arg args; + s32 api_status; +}; + +/* + * This ioctl interface for sharedregion module + */ +int sharedregion_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _SHAREDREGION_IOCTL_H */ + + diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr.h b/arch/arm/plat-omap/include/syslink/sysmemmgr.h new file mode 100644 index 000000000000..34c3b4182288 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmemmgr.h @@ -0,0 +1,179 @@ +/* + * sysmemmgr.h + * + * Manager for the Slave system memory. Slave system level memory is allocated + * through this module. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + + +#ifndef _SYSTEMMEMORYMANAGER_H_ +#define _SYSTEMMEMORYMANAGER_H_ + + +/*! + * @def SYSMEMMGR_MODULEID + * @brief Module identifier for System memory manager. + */ +#define SYSMEMMGR_MODULEID (0xb53d) + +/*! + * @def SYSMEMMGR_STATUSCODEBASE + * @brief Error code base for system memory manager module. + */ +#define SYSMEMMGR_STATUSCODEBASE (SYSMEMMGR_MODULEID << 12u) + +/*! + * @def SYSMEMMGR_MAKE_ERROR + * @brief Macro to make error code. + */ +#define SYSMEMMGR_MAKE_ERROR(x) ((int)(0x80000000 + \ + (SYSMEMMGR_STATUSCODEBASE + \ + (x)))) + +/*! + * @def SYSMEMMGR_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define SYSMEMMGR_MAKE_SUCCESS(x) (SYSMEMMGR_STATUSCODEBASE + (x)) + +/*! + * @def SYSMEMMGR_E_CREATEALLOCATOR + * @brief Static allocator creation failed. + */ +#define SYSMEMMGR_E_CREATEALLOCATOR SYSMEMMGR_MAKE_ERROR(1) + +/*! + * @def SYSMEMMGR_E_CREATELOCK + * @brief Mutex lock creation failed. + */ +#define SYSMEMMGR_E_CREATELOCK SYSMEMMGR_MAKE_ERROR(2) + +/*! + * @def SYSMEMMGR_E_INVALIDSTATE + * @brief Module is not initialized. + */ +#define SYSMEMMGR_E_INVALIDSTATE SYSMEMMGR_MAKE_ERROR(3) + +/*! + * @def SYSMEMMGR_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define SYSMEMMGR_E_INVALIDARG SYSMEMMGR_MAKE_ERROR(4) + +/*! + * @def SYSMEMMGR_E_BPAFREE + * @brief Freeing to buddy allocator failed. + */ +#define SYSMEMMGR_E_BPAFREE SYSMEMMGR_MAKE_ERROR(5) + +/*! + * @def SYSMEMMGR_E_MEMORY + * @brief Memory allocation failed. + */ +#define SYSMEMMGR_E_MEMORY SYSMEMMGR_MAKE_ERROR(6) + +/*! + * @def SYSMEMMGR_SUCCESS + * @brief Operation successful. + */ +#define SYSMEMMGR_SUCCESS SYSMEMMGR_MAKE_SUCCESS(0) + +/*! + * @def SYSMEMMGR_S_ALREADYSETUP + * @brief Module already initialized. + */ +#define SYSMEMMGR_S_ALREADYSETUP SYSMEMMGR_MAKE_SUCCESS(1) + +/*! + * @def SYSMEMMGR_S_DRVALREADYOPENED + * @brief Internal OS Driver is already opened. + */ +#define SYSMEMMGR_S_DRVALREADYOPENED SYSMEMMGR_MAKE_SUCCESS(2) + +/*! + * @brief Configuration data structure of system memory manager. + */ +struct sysmemmgr_config { + u32 sizeof_valloc; + /* Total size for virtual memory allocation */ + u32 sizeof_palloc; + /* Total size for physical memory allocation */ + u32 static_phys_base_addr; + /* Physical address of static memory region */ + u32 static_virt_base_addr; + /* Virtual address of static memory region */ + u32 static_mem_size; + /* size of static memory region */ + u32 page_size; + /* Page size */ + u32 event_no; + /* Event number to be used */ +}; + +/*! + * @brief Flag used for allocating memory blocks. + */ +enum sysmemmgr_allocflag { + sysmemmgr_allocflag_uncached = 0u, + /* Flag used for allocating uncacheable block */ + sysmemmgr_allocflag_cached = 1u, + /* Flag used for allocating cacheable block */ + sysmemmgr_allocflag_physical = 2u, + /* Flag used for allocating physically contiguous block */ + sysmemmgr_allocflag_virtual = 3u, + /* Flag used for allocating virtually contiguous block */ + sysmemmgr_allocflag_dma = 4u + /* Flag used for allocating DMAable (physically contiguous) block */ +}; + +/*! + * @brief Flag used for translating address. + */ +enum sysmemmgr_xltflag { + sysmemmgr_xltflag_kvirt2phys = 0x0001u, + /* Flag used for converting Kernel virtual address to physical + * address */ + sysmemmgr_xltflag_kvirt2uvirt = 0x0002u, + /* Flag used for converting Kernel virtual address to user virtual + * address */ + sysmemmgr_xltflag_uvirt2phys = 0x0003u, + /* Flag used for converting user virtual address to physical address */ + sysmemmgr_xltflag_uvirt2kvirt = 0x0004u, + /* Flag used for converting user virtual address to Kernel virtual + * address */ + sysmemmgr_xltflag_phys2kvirt = 0x0005u, + /* Flag used for converting physical address to user virtual address */ + sysmemmgr_xltflag_phys2uvirt = 0x0006u + /* Flag used for converting physical address to Kernel virtual + * address */ +}; + + +/* Function prototypes */ +void sysmemmgr_get_config(struct sysmemmgr_config *config); + +int sysmemmgr_setup(struct sysmemmgr_config *params); + +int sysmemmgr_destroy(void); + +int sysmemmgr_attach(u16 slave_id); + +void *sysmemmgr_alloc(u32 size, enum sysmemmgr_allocflag flag); + +int sysmemmgr_free(void *blk, u32 size, enum sysmemmgr_allocflag flag); + +void *sysmemmgr_translate(void *srcAddr, enum sysmemmgr_xltflag flag); + + +#endif /* _SYSTEMMEMORYMANAGER_H_ */ diff --git a/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h new file mode 100644 index 000000000000..4b0d99615560 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmemmgr_ioctl.h @@ -0,0 +1,130 @@ +/* + * sysmemmgr_ioctl.h + * + * Definitions of sysmemmgr driver types and structures.. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSMEMMGR_IOCTL_H_ +#define _SYSMEMMGR_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <sysmgr.h> + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for sysmemmgr + * ---------------------------------------------------------------------------- + */ +/* IOC Magic Number for sysmemmgr */ +#define SYSMEMMGR_IOC_MAGIC IPC_IOC_MAGIC + +/* IOCTL command numbers for sysmemmgr */ +enum sysmemmgr_drv_cmd { + SYSMEMMGR_GETCONFIG = SYSMEMMGR_BASE_CMD, + SYSMEMMGR_SETUP, + SYSMEMMGR_DESTROY, + SYSMEMMGR_ALLOC, + SYSMEMMGR_FREE, + SYSMEMMGR_TRANSLATE +}; + +/* Command for sysmemmgr_getConfig */ +#define CMD_SYSMEMMGR_GETCONFIG \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_GETCONFIG, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_setup */ +#define CMD_SYSMEMMGR_SETUP \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_SETUP, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_destroy */ +#define CMD_SYSMEMMGR_DESTROY \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_DESTROY, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_alloc */ +#define CMD_SYSMEMMGR_ALLOC \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_ALLOC, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_free */ +#define CMD_SYSMEMMGR_FREE \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_FREE, \ + struct sysmemmgr_cmd_args) + +/* Command for sysmemmgr_translate */ +#define CMD_SYSMEMMGR_TRANSLATE \ + _IOWR(SYSMEMMGR_IOC_MAGIC, SYSMEMMGR_TRANSLATE, \ + struct sysmemmgr_cmd_args) + + +/* ---------------------------------------------------------------------------- + * Command arguments for sysmemmgr + * ---------------------------------------------------------------------------- + */ +/* Command arguments for sysmemmgr */ +struct sysmemmgr_cmd_args { + union { + struct { + struct sysmemmgr_config *config; + } get_config; + + struct { + struct sysmemmgr_config *config; + } setup; + + struct { + u32 size; + void *buf; + void *phys; + void *kbuf; + enum sysmemmgr_allocflag flags; + } alloc; + + struct { + u32 size; + void *buf; + void *phys; + void *kbuf; + enum sysmemmgr_allocflag flags; + } free; + + struct { + void *buf; + void *ret_ptr; + enum sysmemmgr_xltflag flags; + } translate; + } args; + + s32 api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for sysmemmgr module + * ---------------------------------------------------------------------------- + */ +/* ioctl interface function for sysmemmgr */ +int sysmemmgr_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* SYSMEMMGR_DRVDEFS_H_0xF414 */ diff --git a/arch/arm/plat-omap/include/syslink/sysmgr.h b/arch/arm/plat-omap/include/syslink/sysmgr.h new file mode 100644 index 000000000000..19fab220b2c4 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmgr.h @@ -0,0 +1,182 @@ +/* + * sysmgr.h + * + * Defines for System manager. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSMGR_H_ +#define _SYSMGR_H_ + + +/* Module headers */ +#include <multiproc.h> +#include <gatepeterson.h> +#include <sharedregion.h> +#include <listmp.h> +#include <listmp_sharedmemory.h> +#include <messageq.h> +#include <messageq_transportshm.h> +#include <notify.h> +#include <notify_ducatidriver.h> +#include <nameserver.h> +#include <nameserver_remote.h> +#include <nameserver_remotenotify.h> +#include <procmgr.h> +#include <heap.h> +#include <heapbuf.h> +#include <sysmemmgr.h> + + +/*! + * @def SYSMGR_MODULEID + * @brief Unique module ID. + */ +#define SYSMGR_MODULEID (0xF086) + + +/* ============================================================================= + * Module Success and Failure codes + * ============================================================================= + */ +/*! + * @def SYSMGR_STATUSCODEBASE + * @brief Error code base for System manager. + */ +#define SYSMGR_STATUSCODEBASE (SYSMGR_MODULEID << 12u) + +/*! + * @def SYSMGR_MAKE_FAILURE + * @brief Macro to make error code. + */ +#define SYSMGR_MAKE_FAILURE(x) ((s32)(0x80000000 + \ + (SYSMGR_STATUSCODEBASE + \ + (x)))) + +/*! + * @def SYSMGR_MAKE_SUCCESS + * @brief Macro to make success code. + */ +#define SYSMGR_MAKE_SUCCESS(x) (SYSMGR_STATUSCODEBASE + (x)) + +/*! + * @def SYSMGR_E_INVALIDARG + * @brief Argument passed to a function is invalid. + */ +#define SYSMGR_E_INVALIDARG SYSMGR_MAKE_FAILURE(1) + +/*! + * @def SYSMGR_E_MEMORY + * @brief Memory allocation failed. + */ +#define SYSMGR_E_MEMORY SYSMGR_MAKE_FAILURE(2) + +/*! + * @def SYSMGR_E_FAIL + * @brief General failure. + */ +#define SYSMGR_E_FAIL SYSMGR_MAKE_FAILURE(3) + +/*! + * @def SYSMGR_E_INVALIDSTATE + * @brief Module is in invalid state. + */ +#define SYSMGR_E_INVALIDSTATE SYSMGR_MAKE_FAILURE(4) + +/*! + * @def SYSMGR_E_OSFAILURE + * @brief Failure in OS call. + */ +#define SYSMGR_E_OSFAILURE SYSMGR_MAKE_FAILURE(5) + +/*! + * @def SYSMGR_S_ALREADYSETUP + * @brief Module is already initialized. + */ +#define SYSMGR_S_ALREADYSETUP SYSMGR_MAKE_SUCCESS(1) + +/*! + * @def SYSMGR_CMD_SCALABILITY + * @brief Command ID for scalability info. + */ +#define SYSMGR_CMD_SCALABILITY (0x00000000) + +/*! + * @def SYSMGR_CMD_SHAREDREGION_ENTRY_BASE + * @brief Base of command IDs for entries used by Shared region. + */ +#define SYSMGR_CMD_SHAREDREGION_ENTRY_START (0x00000001) +#define SYSMGR_CMD_SHAREDREGION_ENTRY_END (0x00001000) + + +/* ============================================================================= + * Structures & Enums + * ============================================================================= + */ +/*! + * @brief Structure defining config parameters for overall System. + */ +struct sysmgr_config { + struct sysmemmgr_config sysmemmgr_cfg; + /*!< System memory manager config parameter */ + + struct multiproc_config multiproc_cfg; + /*!< Multiproc config parameter */ + + struct gatepeterson_config gatepeterson_cfg; + /*!< Gatepeterson config parameter */ + + struct sharedregion_config sharedregion_cfg; + /*!< SharedRegion config parameter */ + + struct messageq_config messageq_cfg; + /*!< MessageQ config parameter */ + + struct notify_config notify_cfg; + /*!< Notify config parameter */ + + struct proc_mgr_config proc_mgr_cfg; + /*!< Processor manager config parameter */ + + struct heapbuf_config heapbuf_cfg; + /*!< Heap Buf config parameter */ + + struct listmp_config listmp_sharedmemory_cfg; + /*!< ListMPSharedMemory config parameter */ + + struct messageq_transportshm_config messageq_transportshm_cfg; + /*!< MessageQTransportShm config parameter */ + + struct notify_ducatidrv_config notify_ducatidrv_cfg; + /*!< NotifyDriverShm config parameter */ + + struct nameserver_remotenotify_config nameserver_remotenotify_cfg; + /*!< NameServerRemoteNotify config parameter */ +}; + + +/* ============================================================================= + * APIs + * ============================================================================= + */ +/* Function to initialize the parameter structure */ +void sysmgr_get_config(struct sysmgr_config *config); + +/* Function to initialize sysmgr module */ +s32 sysmgr_setup(const struct sysmgr_config *config); + +/* Function to Finalize sysmgr module */ +s32 sysmgr_destroy(void); + + +#endif /* ifndef SYSMGR_H_0xF086 */ diff --git a/arch/arm/plat-omap/include/syslink/sysmgr_ioctl.h b/arch/arm/plat-omap/include/syslink/sysmgr_ioctl.h new file mode 100644 index 000000000000..03db7b9511a2 --- /dev/null +++ b/arch/arm/plat-omap/include/syslink/sysmgr_ioctl.h @@ -0,0 +1,100 @@ +/* + * sysmgr_ioctl.h + * + * Definitions of sysmgr driver types and structures.. + * + * Copyright (C) 2008-2009 Texas Instruments, Inc. + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +#ifndef _SYSMGR_IOCTL_H_ +#define _SYSMGR_IOCTL_H_ + +/* Standard headers */ +#include <linux/types.h> + +/* Syslink headers */ +#include <ipc_ioctl.h> +#include <sysmgr.h> + + +/* ============================================================================= + * Macros and types + * ============================================================================= + */ +/* ---------------------------------------------------------------------------- + * IOCTL command IDs for sysmgr + * ---------------------------------------------------------------------------- + */ +/* IOC Magic Number for sysmgr */ +#define SYSMGR_IOC_MAGIC IPC_IOC_MAGIC + +/* IOCTL command numbers for sysmgr */ +enum sysmgr_drv_cmd { + SYSMGR_SETUP = SYSMGR_BASE_CMD, + SYSMGR_DESTROY, + SYSMGR_LOADCALLBACK, + SYSMGR_STARTCALLBACK, + SYSMGR_STOPCALLBACK +}; + +/* Command for sysmgr_setup */ +#define CMD_SYSMGR_SETUP \ + _IOWR(SYSMGR_IOC_MAGIC, SYSMGR_SETUP, \ + struct sysmgr_cmd_args) + +/* Command for sysmgr_destroy */ +#define CMD_SYSMGR_DESTROY \ + _IOWR(SYSMGR_IOC_MAGIC, SYSMGR_DESTROY, \ + struct sysmgr_cmd_args) + +/* Command for load callback */ +#define CMD_SYSMGR_LOADCALLBACK \ + _IOWR(SYSMGR_IOC_MAGIC, SYSMGR_LOADCALLBACK, \ + struct sysmgr_cmd_args) + +/* Command for load callback */ +#define CMD_SYSMGR_STARTCALLBACK \ + _IOWR(SYSMGR_IOC_MAGIC, SYSMGR_STARTCALLBACK, \ + struct sysmgr_cmd_args) + +/* Command for stop callback */ +#define CMD_SYSMGR_STOPCALLBACK \ + _IOWR(SYSMGR_IOC_MAGIC, SYSMGR_STOPCALLBACK, \ + struct sysmgr_cmd_args) + + +/* ---------------------------------------------------------------------------- + * Command arguments for sysmgr + * ---------------------------------------------------------------------------- + */ +/* Command arguments for sysmgr */ +struct sysmgr_cmd_args { + union { + struct { + struct sysmgr_config *config; + } setup; + + int proc_id; + } args; + + s32 api_status; +}; + +/* ---------------------------------------------------------------------------- + * IOCTL functions for sysmgr module + * ---------------------------------------------------------------------------- + */ +/* ioctl interface function for sysmgr */ +int sysmgr_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long args); + +#endif /* _SYSMGR_IOCTL_H_ */ |